82801DB Datasheet, PDF (41/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Signal Description
Table 2-5. PCI Interface Signals (Sheet 2 of 3)
Name
Type
Description
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PERR#
REQ[0:4]#
REQ[5]# /
REQ[B]# /
GPIO[1]
Device Select: The ICH4 asserts DEVSEL# to claim a PCI transaction. As an
output, the ICH4 asserts DEVSEL# when a PCI master peripheral attempts an
access to an internal ICH4 address or an address destined for the hub
I/O interface (main memory or AGP). As an input, DEVSEL# indicates the
response to an ICH4-initiated transaction on the PCI bus. DEVSEL# is tri-
stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated by the
ICH4 until driven by a Target device.
Cycle Frame: The current Initiator drives FRAME# to indicate the beginning
and duration of a PCI transaction. While the Initiator asserts FRAME#, data
I/O
transfers continue. When the Initiator negates FRAME#, the transaction is in
the final data phase. FRAME# is an input to the ICH4 when the ICH4 is the
Target, and FRAME# is an output from the ICH4 when the ICH4 is the Initiator.
FRAME# remains tri-stated by the ICH4 until driven by an Initiator.
Initiator Ready: IRDY# indicates the ICH4's ability, as an Initiator, to complete
the current data phase of the transaction. It is used in conjunction with TRDY#.
A data phase is completed on any clock that both IRDY# and TRDY# are
I/O
sampled asserted. During a write, IRDY# indicates the ICH4 has valid data
present on AD[31:0]. During a read, it indicates the ICH4 is prepared to latch
data. IRDY# is an input to the ICH4 when the ICH4 is the Target and an output
from the ICH4 when the ICH4 is an Initiator. IRDY# remains tri-stated by the
ICH4 until driven by an Initiator.
Target Ready: TRDY# indicates the ICH4's ability, as a Target, to complete the
current data phase of the transaction. TRDY# is used in conjunction with
IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled
asserted. During a read, TRDY# indicates that the ICH4, as a Target, has
I/O placed valid data on AD[31:0]. During a write, TRDY# indicates that the ICH4,
as a Target, is prepared to latch data. TRDY# is an input to the ICH4 when the
ICH4 is the Initiator and an output from the ICH4 when the ICH4 is a Target.
TRDY# is tri-stated from the leading edge of PCIRST#. TRDY# remains tri-
stated by the ICH4 until driven by a Target.
Stop: STOP# indicates that the ICH4, as a Target, is requesting the Initiator to
stop the current transaction. STOP# causes the ICH4, as an Initiator, to stop
I/O the current transaction. STOP# is an output when the ICH4 is a Target and an
input when the ICH4 is an Initiator. STOP# is tri-stated from the leading edge of
PCIRST#. STOP# remains tri-stated until driven by the ICH4.
Calculated/Checked Parity: PAR uses “even” parity calculated on 36 bits,
AD[31:0] plus C/BE[3:0]#. “Even” parity means that the ICH4 counts the
number of 1s within the 36 bits plus PAR and the sum is always even. The
ICH4 always calculates PAR on 36 bits regardless of the valid byte enables.
The ICH4 generates PAR for address and data phases and only guarantees
PAR to be valid one PCI clock after the corresponding address or data phase.
I/O
The ICH4 drives and tri-states PAR identically to the AD[31:0] lines except that
the ICH4 delays PAR by exactly one PCI clock. PAR is an output during the
address phase (delayed one clock) for all ICH4 initiated transactions. PAR is
an output during the data phase (delayed one clock) when the ICH4 is the
Initiator of a PCI write transaction, and when it is the Target of a read
transaction. ICH4 checks parity when it is the Target of a PCI write transaction.
If a parity error is detected, the ICH4 will set the appropriate internal status bits,
and has the option to generate an NMI# or SMI#.
Parity Error: An external PCI device drives PERR# when it receives data that
I/O
has a parity error. The ICH4 drives PERR# when it detects a parity error. The
ICH4 can either generate an NMI# or SMI# upon detecting a parity error (either
detected internally or reported via the PERR# signal).
PCI Requests: The ICH4 supports up to 6 masters on the PCI bus. REQ[5]# is
muxed with PC/PCI REQ[B]# (must choose one or the other, but not both). If
I
not used for PCI or PC/PCI, REQ[5]#/REQ[B]# can instead be used as
GPIO[1].
NOTE: REQ[0]# is programmable to have improved arbitration latency for
supporting PCI-based 1394 controllers.
Intel^® 82801DB ICH4 Datasheet
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