82801DB Datasheet, PDF (448/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

EHCI Controller Registers (D29:F7)
Bit
Description
28
27:17
16
15:12
ENABLED_CNT — R/W.
0 = Software can clear this bit by writing a 0 to it. Hardware clears the bit for the same conditions
where the Port Enable/Disable Change bit (in the PORTSC register) is set. (Default)
1 = Enable debug port for operation. Software can directly set this bit if the port is already enabled
in the associated Port Status and Control register (this is enforced by the hardware).
Reserved
DONE_STS — R/WC.
0 = Not Done (Default). Software clears this bit by writing a 1 to it.
1 = This bit is set by hardware to indicate that the request is complete.
LINK_ID_STS — RO. Hardwired to 0000. This field identifies the link interface. It is hardwired to 0h
to indicate that it is a USB Debug Port.
11 Reserved. This bit will return 0 when read. Writes will have no effect.
IN_USE_CNT — R/W. (This bit has no affect on hardware.)
10
0 = Not in Use. Cleared by software to indicate that the port is free and may be used by other
software. (Default)
1 = In Use. Set by software to indicate that the port is in use.
EXCEPTION_STS — RO. Default=000b This field indicates the exception when the
ERROR_GOOD#_STS bit is set. This field should be ignored if the ERROR_GOOD#_STS bit is 0.
000 =No Error. Note: this should not be seen, since this field should only be checked if there is an
error.
9:7 _{001 =Transaction error: indicates the USB EHCI transaction had an error (CRC, bad PID, timeout,}
etc.)
010 =HW error. Request was attempted (or in progress) when port was suspended or reset.
All Others = Reserved
ERROR_GOOD#_STS — RO.
6
0 = Hardware clears this bit upon the proper completion of a read or write. (Default)
1 = Error Occurred. The hardware sets this bit to indicate that an error has occurred. Details on
the nature of the error are provided in the Exception field.
GO_CNT — WO.
5
0 = Hardware clears this bit when hardware sets the DONE_STS bit. (Default)
1 = Causes hardware to perform a read or write request. Writing a 1 to this bit when it is already
set may result in undefined behavior.
WRITE_READ#_CNT — R/W.
4
0 = Read. Software clears this bit to indicate that the current request is a read. (Default)
1 = Write. Software sets this bit to indicate that the current request is a write.
DATA_LEN_CNT — R/W. This field is used to indicate the size of the data to be transferred.
(default = 0h).
For write operations, this field is set by software to indicate to the hardware how many bytes of data
in Data Buffer are to be transferred to the console. A value of 0h indicates that a zero-length packet
should be sent. A value of 1–8h indicates 1–8 bytes are to be transferred. Values 9–Fh are illegal
and how hardware behaves if used is undefined.
3:0
For read operations, this field is set by hardware to indicate to software how many bytes in Data
Buffer are valid in response to a read operation. A value of 0h indicates that a zero length packet
was returned and the state of Data Buffer is not defined. A value of 1–8 indicates 1–8 bytes were
received. Hardware does not return values 9–Fh.
The transferring of data always starts with byte 0 in the data area and moves toward byte 7 until the
transfer size is reached.
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Intel^® 82801DB ICH4 Datasheet