82801DB Datasheet, PDF (439/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

EHCI Controller Registers (D29:F7)
Bit
Description
Frame List Rollover — R/WC.
0 = No rollover.
3 _{1 = Frame List Rollover. The Host controller sets this bit to a 1 when the Frame List Index (see}
Section) rolls over from its maximum value to zero. Since the ICH4 only supports the 1024-
entry Frame List Size, the Frame List Index rolls over every time FRNUM[13] toggles.
Port Change Detect — R/WC.
0 = Not Detected.
2 _{1 = Port Change Detected. The Host controller sets this bit to a 1 when any port for which the Port}
Owner bit is set to 0 has a change bit transition from 0 to 1 or a Force Port Resume bit transition
from 0 to 1 as a result of a J-K transition detected on a suspended port.
USB Error Interrupt (USBERRINT) — R/WC.
0 = No Error.
1 ^{1 = Error Condition. The Host controller sets this bit to 1 when completion of a USB transaction}
results in an error condition (e.g., error counter underflow). If the TD on which the error interrupt
occurred also had its IOC bit set, both this bit and Bit 0 are set. See the EHCI specification for a
list of the USB errors that will result in this interrupt being asserted.
USB Interrupt (USBINT) — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = The Host controller sets this bit to 1 when one of the following occurs:
0
• The cause of an interrupt is a completion of a USB transaction whose Transfer Descriptor
had its IOC bit set.
• The Host controller also sets this bit to 1 when a short packet is detected (actual number of
bytes received was less than the expected number of bytes).
Intel^® 82801DB ICH4 Datasheet
439