82801DB Datasheet, PDF (160/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
Table 5-51. GPIO Implementation (Sheet 2 of 2)
GPIO
Type
GPO[16]
Output
Only
GPO[17]
Output
Only
GPO[18]
Output
Only
GPO[19]
Output
Only
GPO[20]
Output
Only
GPO[21]
Output
Only
GPO[22]
Output
Only
GPIO[23
Output
Only
GPIO[24]
I/O
GPIO[25]
I/O
GPIO[26]
N/A
GPIO[27:28] I/O
GPIO[29:31] N/A
GPIO[32:43] I/O
Alternate
Function ⁽¹⁾
GNT[A]#
GNT[B]# or
GNT[5]#
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Unmuxed
N/A
Unmuxed
N/A
Unmuxed
Power
Well
Tolerant
Core
3.3 V
Core
3.3 V
Core
3.3 V
Core
3.3 V
Core
3.3 V
Core
3.3 V
Core
3.3 V
Core
3.3 V
Resume 3.3 V
Resume 3.3 V
N/A
Resume 3.3 V
N/A
Core
3.3 V
Notes
• Output controlled via GP_LVL register
bit 16.
• TTL driver output
• Output controlled via GP_LVL register
bit 17.
• TTL driver output
• Output controlled via GP_LVL register
bits [18:19].
• TTL driver output
• Output controlled via GP_LVL register
bits [18:19].
• TTL driver output
• Output controlled via GP_LVL register
bit 20.
• TTL driver output
• This GPO defaults high.
• Output controlled via GP_LVL register
bit 21.
• TTL driver output
• Output controlled via GP_LVL register
bit [22].
• Open-drain output
• Output controlled via GP_LVL register
bit [23].
• TTL driver output
• Input active status read from GP_LVL
register bit 24.
• Output controlled via GP_LVL register
bit 24.
• TTL driver output
• Blink enabled via GPO_BLINK register
bit 25.
• Input active status read from GP_LVL
register bit 25
• Output controlled via GP_LVL register
bit 25.
• TTL driver output
• Not implemented
• Input active status read from GP_LVL
register bits [27:28]
• Output controlled via GP_LVL register
bits [27:28]
• TTL driver output
• Not implemented
NOTES:
1. All GPIOs default to their alternate function.
2. All inputs are sticky. The status bit remains set as long as the input was asserted for 2 clocks. GPIs are
sampled on PCI clocks in S0/S1. GPIs are sampled on RTC clocks in S3/S4/S5 .
3. GPIO[0:7] are 5 V tolerant, and all GPIs can be routed to cause an SCI or SMI#.
4. If GPIO_USE_SEL bit 1 is set to 1 and GEN_CNT bit 25 is also set to 1 then REQ/GNT[5]# is enabled. See
Section 9.1.22.
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Intel^® 82801DB ICH4 Datasheet