82801DB Datasheet, PDF (557/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Testability
Table 19-7. XOR Chain 4-2
Pin Name
PME#
GPIO25
GPIO12
GPIO27
PCIRST#
GPIO13
GPIO28
PWRBTN#
SYS_RESET#
SMLINK1
TP[0]
GPIO24
SUSCLK
SUS_STAT#/
LPCPD#
SMLINK0
SLP_S3#
SMBDATA
SMBCLK
SMBALERT#/
GPIO11
CLK48
OC0#
OC2#
OC5#
OC1#
OC3#
OC4#
Ball #
W2
V2
V5
W1
U5
W3
W4
AA1
Y3
AB1
AB2
AC2
AA4
Notes
Top of XOR Chain
2nd signal in XOR
AB3
AC3
Y4
AB4
AC4
AA5
F19
B15
A15
D14
C14
B14
A14
Pin Name
AC_RST#
USBP0P
USBP0N
USBP1P
USBP1N
USBP2P
USBP2N
USBP3P
USBP3N
USBP4P
USBP4N
USBP5P
USBP5N
LAN_TXD2
LAN_CLK
EE_DIN
LAN_RXD2
LAN_RSTSYNC
EE_CS
LAN_TXD0
LAN_RXD0
LAN_TXD1
EE_DOUT
LAN_RXD1
EE_SHCLK
Ball #
C13
C20
D20
A21
B21
C18
D18
A19
B19
C16
D16
A17
B17
A12
C11
D11
A11
B11
D10
B10
A10
C10
A8
A9
C12
AC_SDIN1
NOTES:
1. RTCRST# asserted for 7 PCI clocks while PWROK active.
2
Table 19-8. XOR Chain 6
Pin Name
Ball #
Notes⁽¹⁾
Pin Name
RTCX1
AC7 Top of XOR Chain
A13
Ball #
TP[0]
AB2
NOTES:
1. RTCRST# asserted for 52 PCI clocks while PWROK active.
2
Notes⁽¹⁾
XOR Chain 4-2
OUTPUT
Notes⁽¹⁾
XOR Chain 6
OUTPUT
Intel^® 82801DB ICH4 Datasheet
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