82801DB Datasheet, PDF (44/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Signal Description
2.7
LPC Interface
Table 2-7. LPC Interface Signals
Name
LAD[3:0] /
FWH[3:0]
LFRAME# /
FWH[4]
LDRQ[1:0]#
Type
I/O
Description
LPC Multiplexed Command, Address, Data: For the LAD[3:0] signals,
internal pull-ups are provided.
O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.
LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request
I
DMA or bus master access. These signals are typically connected to an
external Super I/O device. An internal pull-up resistor is provided on these
signals.
2.8
Interrupt Interface
Table 2-8. Interrupt Signals
Name
SERIRQ
PIRQ[D:A]#
PIRQ[H:E]# /
GPIO[5:2]
IRQ[14:15]
APICCLK
APICD[1:0]
Type
I/O
I/OD
I/OD
I
I
I/OD
Description
Serial Interrupt Request: This pin implements the serial interrupt protocol.
PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed
to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt
Steering section. Each PIRQx# line has a separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC in the
following fashion: PIRQ[A]# is connected to IRQ16, PIRQ[B]# to IRQ17,
PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19. This frees the legacy interrupts.
PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed
to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt
Steering section. Each PIRQx# line has a separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC in the
following fashion: PIRQ[E]# is connected to IRQ20, PIRQ[F]# to IRQ21,
PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23. This frees the legacy interrupts. If
not needed for interrupts, these signals can be used as GPIO.
Interrupt Request 14:15: These interrupt inputs are connected to the IDE
drives. IRQ14 is used by the drives connected to the Primary controller and
IRQ15 is used by the drives connected to the Secondary controller.
APIC Clock: This clock operates up to 33.33 MHz.
APIC Data: These bi-directional open drain signals are used to send and
receive data over the APIC bus. As inputs the data is valid on the rising edge of
APICCLK. As outputs, new data is driven from the rising edge of the APICCLK.
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Intel^® 82801DB ICH4 Datasheet