82801DB Datasheet, PDF (458/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

SMBus Controller Registers (D31:F3)
13.2.2 HST_CNT—Host Control Register
Register Offset: 02h
Default Value: 00h
Attribute:
Size:
R/W, WO
8-bits
Note: A read to this register will clear the byte pointer of the 32-byte buffer.
Bit
Description
PEC_EN — R/W.
0 = SMBus host controller does not perform the transaction with the PEC phase appended.
7 ^{1 = Causes the host controller to perform the SMBus transaction with the Packet Error Checking}
phase appended. For writes, the value of the PEC byte is transferred from the PEC Register.
For reads, the PEC byte is loaded in to the PEC Register. This bit must be written prior to the
write in which the START bit is set.
START — WO.
0 = This bit will always return 0 on reads. The HOST_BUSY bit in the Host Status register (offset
6
00h) can be used to identify when the ICH4 has finished the command.
1 = Writing a 1 to this bit initiates the command described in the SMB_CMD field. All registers
should be setup prior to writing a 1 to this bit position.
LAST_BYTE — WO. This bit is used for Block Read commands.
1 = Software sets this bit to indicate that the next byte will be the last byte to be received for the
block. This causes the ICH4 to send a NACK (instead of an ACK) after receiving the last byte.
5
NOTE: Once the SECOND_TO_STS bit in TCO2_STS register (D31:F0, TCOBASE+6h, bit 1) is
set, the LAST_BYTE bit also gets set. While the SECOND_TO_STS bit is set, the
LAST_BYTE bit cannot be cleared. This prevents the ICH4 from running some of the
SMBus commands (Block Read/Write, I²C Read, Block I²C Write).
SMB_CMD — R/W. The bit encoding below indicates which command the ICH4 is to perform. If
enabled, the ICH4 will generate an interrupt or SMI# when the command has completed If the value
is for a non-supported or reserved command, the ICH4 will set the device error (DEV_ERR) status
bit and generate an interrupt when the START bit is set. The ICH4 will perform no command, and will
not operate until DEV_ERR is cleared.
000 = Quick: The slave address and read/write value (bit 0) are stored in the transmit slave address
register.
001 = Byte: This command uses the transmit slave address and command registers. Bit 0 of the
slave address register determines if this is a read or write command.
010 = Byte Data: This command uses the transmit slave address, command, and DATA0 registers.
Bit 0 of the slave address register determines if this is a read or write command. If it is a read,
the DATA0 register will contain the read data.
011 = Word Data: This command uses the transmit slave address, command, DATA0 and DATA1
registers. Bit 0 of the slave address register determines if this is a read or write command. If it
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is a read, after the command completes, the DATA0 and DATA1 registers will contain the read
data.
100 = Process Call: This command uses the transmit slave address, command, DATA0 and DATA1
registers. Bit 0 of the slave address register determines if this is a read or write command.
After the command completes, the DATA0 and DATA1 registers will contain the read data.
101 = Block: This command uses the transmit slave address, command, DATA0 registers, and the
Block Data Byte register. For block write, the count is stored in the DATA0 register and
indicates how many bytes of data will be transferred. For block reads, the count is received
and stored in the DATA0 register. Bit 0 of the slave address register selects if this is a read or
write command. For writes, data is retrieved from the first n (where n is equal to the specified
count) addresses of the SRAM array. For reads, the data is stored in the Block Data Byte
register.
110 = I²C Read: This command uses the transmit slave address, command, DATA0, DATA1
registers, and the Block Data Byte register. The read data is stored in the Block Data Byte
register. The ICH4 will continue reading data until the NAK is received.
111 = Reserved
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Intel^® 82801DB ICH4 Datasheet