82801DB Datasheet, PDF (201/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.17.7 USB EHCI Power Management
5.17.7.1
Pause Feature
This feature allows platforms (especially mobile systems) to dynamically enter low-power states
during brief periods when the system is idle (i.e., between keystrokes). This is useful for enabling
power management features like C3, C4, and Intel SpeedStep technology in the ICH4. The policies
for entering these states typically are based on the recent history of system bus activity to
incrementally enter deeper power management states. Normally, when the EHC is enabled, it
regularly accesses main memory while traversing the DMA schedules looking for work to do; this
activity is viewed by the power management software as a non-idle system, thus preventing the
power managed states to be entered. Suspending all of the enabled ports can prevent the memory
accesses from occurring, but there is an inherent latency overhead with entering and exiting the
suspended state on the USB ports that makes this unacceptable for the purpose of dynamic power
management. As a result, the EHCI software drivers are allowed to pause the EHC’s DMA engines
when it knows that the traffic patterns of the attached devices can afford the delay. The pause only
prevents the EHC from generating memory accesses; the SOF packets continue to be generated on
the USB ports (unlike the suspended state).
5.17.7.2
Suspend Feature
The Enhanced Host Controller Interface (EHCI) for Universal Serial Bus Specification describes
the details of Port Suspend and Resume in detail in Section 4.3.
5.17.7.3
ACPI Device States
The USB EHCI function only supports the D0 and D3 PCI Power Management states. Notes
regarding the ICH4 implementation of the Device States:
• The EHC hardware does not inherently consume any more power when it is in the D0 state
than it does in the D3 state. However, software is required to suspend or disable all ports prior
to entering the D3 state such that the maximum power consumption is reduced.
• In the D0 state, all implemented EHC features are enabled.
• In the D3 state, accesses to the EHC memory-mapped I/O range will master abort. Note that,
since the Debug Port uses the same memory range, the Debug Port is only operational when
the EHC is in the D0 state.
• In the D3 state, the EHC interrupt must never assert for any reason. The internal PME# signal
is used to signal wake events, etc.
• When the Device Power State field is written to D0 from D3, an internal reset is generated. See
section EHC Resets for general rules on the effects of this reset.
• Attempts to write any other value into the Device Power State field other than 00b (D0 state)
and 11b (D3 state) will complete normally without changing the current value in this field.
Intel^® 82801DB ICH4 Datasheet
201