82801DB Datasheet, PDF (419/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

EHCI Controller Registers (D29:F7)
12.1.3
PCICMD—PCI Command Register (USB EHCI—D29:F7)
Address Offset: 04–05h
Default Value: 0000h
Attribute: R/W, RO
Size:
16 bits
Bit
Description
15:10 Reserved
9 Fast Back to Back Enable (FBE) — RO. Reserved as 0.
SERR# Enable (SERR_EN) — R/W.
0 = Disables EHC’s capability to generate an SERR#.
8 _{1 = The Enhanced Host Controller (EHC) is capable of generating (internally) SERR# when it}
receive a completion status other than “successful” for one of its DMA-initiated memory reads
on the hub interface (and subsequently on its internal interface).
7 Wait Cycle Control (WCC) — RO. Reserved as 0.
6 Parity Error Response (PER) — RO. Reserved as 0.
5 VGA Palette Snoop (VPS) — RO. Reserved as 0.
4 Postable Memory Write Enable (PMWE) — RO. Reserved as 0.
3 Special Cycle Enable (SCE) — RO. Reserved as 0.
Bus Master Enable (BME) — R/W.
2 0 = Disables this functionality.
1 = Enables the ICH4 can act as a master on the PCI bus for USB transfers.
Memory Space Enable (MSE) — R/W. This bit controls access to the USB EHCI Memory Space
registers.
1 0 = Disables this functionality.
1 = Enables accesses to the USB EHCI registers. The Base Address register for USB EHCI should
be programmed before this bit is set.
0 I/O Space Enable (IOSE) — RO. Reserved as 0.
Intel^® 82801DB ICH4 Datasheet
419