82801DB Datasheet, PDF (482/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

AC ’97 Audio Controller Registers (D31:F5)
Table 14-3. Native Audio Bus Master Control Registers (Sheet 2 of 2)
Offset
5Ah
5Bh
60–63
64h
65h
66–67h
68–69h
6Ah
6Bh
80h
Mnemonic
PI2_PIV
PI2_CR
SP_BAR
SP_CIV
SP_LVI
SP_SR
SP_PICB
SP_PIV
SP_CR
SDM
Name
PCM In 2 Prefetched Index Value
PCM In 2 Control Register
S/PDIF Buffer Descriptor List Base Address
S/PDIF Current Index Value
S/PDIF Last Valid Index
S/PDIF Status Register
S/PDIF Position In Current Buffer
S/PDIF Prefetched Index Value
S/PDIF Control Register
SData_IN Map
Default
00h
00h
00000000h
00h
00h
0001h
0000h
00h
00h
00h
Access
RO
R/W
R/W
RO
R/W
R/W
RO
RO
R/W
R/W, RO
Note: Internal reset as a result of D3_HOT to D0 transition will reset all the core well registers except the
registers shared with the AC ’97 Modem (GCR, GSR, CASR). All resume well registers will not be
reset by the D3_HOT to D0 transition.
Core Well registers and bits NOT reset by the D3_HOT to D0 transition:
• offset 2Ch–2Fh – bits[6:0] Global Control (GLOB_CNT)
• offset 30h–33h – bits[29,15,11:10,0] Global Status (GLOB_STA)
• offset 34h – Codec Access Semaphore Register (CAS)
Resume Well registers and bits will NOT be reset by the D3_HOT to D0 transition:
• offset 30h–33h – bits[17:16] Global Status (GLOB_STA)
14.2.1
x_BDBAR—Buffer Descriptor Base Address Register
I/O Address:
Default Value:
Lockable:
NABMBAR + 00h (PIBDBAR), Attribute:
NABMBAR + 10h (POBDBAR),
NABMBAR + 20h (MCBDBAR)
MBBAR + 40h (MC2BDBAR)
MBBAR + 50h (PI2BDBAR)
MBBAR + 60h (SPBAR)
00000000h
Size:
No
Power Well:
R/W
32 bits
Core
Software can read the register at offset 00h by performing a single 32 bit read from address offset
00h. Reads across DWord boundaries are not supported.
Bit
Description
Buffer Descriptor Base Address [31:3] — R/W. These bits represent address bits 31:3. The data
31:3 should be aligned on 8 byte boundaries. Each buffer descriptor is 8 bytes long and the list can
contain a maximum of 32 entries.
2:0 Hardwired to 0.
482
Intel^® 82801DB ICH4 Datasheet