82801DB Datasheet, PDF (137/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.12.2 System Power Planes
The system has several independent power planes, as described in Table 5-37. Note that when a
particular power plane is shut off, it should go to a 0 V level.
s
Table 5-37. System Power Plane
Plane
Processor
MAIN
MEMORY
DEVICE[n]
Controlled
By
SLP_S3#
signal
SLP_S3#
signal
SLP_S4#
signal
GPIO
Description
The SLP_S3# signal can be used to cut the processor’s power completely
When SLP_S3# goes active, power can be shut off to any circuit not required
to wake the system from the S3 state. Since the S3 state requires that the
memory context be preserved, power must be retained to the main memory.
The processor, devices on the PCI bus, LPC interface downstream hub
interface and AGP will typically be shut off when the Main power plane is
shut, although there may be small subsections powered.
When the SLP_S4# goes active, power can be shut off to any circuit not
required to wake the system from the S4. Since the memory context does
not need to be preserved in the S4 state, the power to the memory can also
be shut down.
Individual subsystems may have their own power plane. For example, GPIO
signals may be used to control the power to disk drives, audio amplifiers, or
the display screen.
5.12.3 Intel^® ICH4 Power Planes
The ICH4 power planes are defined in Section 4.1. Although there are not specific power planes
within the ICH4, there are many interface signals that go to devices that may be powered down.
These include:
• IDE: ICH4 can tri-state or drive low all IDE output signals and shut off input buffers.
• USB: ICH4 can tri-state USB output signals and shut off input buffers if USB wakeup is not
desired
• AC ’97: ICH4 can drive low the outputs and shut off inputs
5.12.4
SMI#/SCI Generation
Upon any SMI# event taking place, ICH4 asserts SMI# to the processor which causes it to enter
SMM space. SMI# remains active until the EOS bit is set. When the EOS bit is set, SMI# goes
inactive for a minimum of 4 PCICLK. If another SMI event occurs, SMI# is driven active again.
The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating system. In
non-APIC systems (which is the default), the SCI IRQ is routed to one of the 8259 interrupts
(IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed to level mode for that
interrupt.
In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or 23. The
interrupt polarity changes depending on whether it is on an interrupt shareable with a PIRQ or not;
(see Section 9.1.11 ACPI Control Register for details.) The interrupt will remain asserted until all
SCI sources are removed.
Intel^® 82801DB ICH4 Datasheet
137