82801DB Datasheet, PDF (344/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.7.5
RST_CNT—Reset Control Register
I/O Address:
Default Value:
Lockable:
CF9h
00h
No
Attribute:
Size:
Power Well:
R/W
8 bit
Core
Bit
Description
7:4 Reserved
Full Reset (FULL_RST) — R/W. This bit is used to determine the states of SLP_S3#, SLP_S4# and
SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1), after PWROK going low
3
(with RSMRST# high), or after two TCO timeouts.
0 = Intel^® ICH4 will keep SLP_S3#, SLP_S4# and SLP_S5# high.
1 = ICH4 will drive SLP_S3#, SLP_S4# and SLP_S5# low for 3–5 seconds.
2
Reset CPU (RST_CPU) — R/W. When this bit transitions from a 0 to a 1, it initiates a hard or soft
reset, as determined by the SYS_RST bit (bit 1 of this register).
System Reset (SYS_RST) — R/W. This bit is used to determine a hard or soft reset to the
processor.
0 = When RST_CPU bit goes from 0 to 1, the ICH4 performs a soft reset by activating INIT# for
1
16 PCI clocks.
1 = When RST_CPU bit goes from 0 to 1, the ICH4 performs a hard reset by activating PCIRST#
for 1 millisecond. It also resets the resume well bits (except for those noted throughout the
EDS). The SLP_S3#, SLP_S4#, and SLP_S5# signals will not go active.
0 Reserved
344
Intel^® 82801DB ICH4 Datasheet