82801DB Datasheet, PDF (198/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.17.3.2
5.17.3.1.2 Write Policies for Periodic DMA
The Periodic DMA engine performs writes for the following reasons.
Memory Structure
iTD Status Write
siTD Status Write
Interrupt Queue Head
Overlay
Interrupt Queue Head
Status Write
Interrupt qTD Status
Write
In Data
Size
(DWords)
1
3
14
Comments
Only the DWord that corresponds to the just-executed microframe’s
status is written. All bytes of the DWord are written.
DWords 0C:17h are written. IOC and Buffer Pointer fields are re-
written with the original value.
Only the 64-bit addressing format is supported. DWords 0C:43h are
written.
54
DWords 14:27h are written.
3
Up to 257
DWords 04:0Fh are written. PID Code, IOC, Buffer Pointers, and Alt.
Next qTD Pointers are re-written with the original value.
The ICH4 breaks data writes down into 16-DWord aligned chunks.
NOTES:
1. The Periodic DMA Engine (PDE) will only generate writes after a transaction is executed on USB.
2. Status writes are always performed after In Data writes for the same transaction.
Asynchronous List Execution
The Asynchronous DMA engine contains buffering for two control structures (two transactions).
By implementing two entries, the EHC is able to pipeline the memory accesses for the next
transaction while executing the current transaction on the USB ports.
5.17.3.2.1 Read Policies for Asynchronous DMA
The Asynchronous DMA engine performs reads for the following structures.
Memory Structure
qTD
Queue Head
Out Data
Size (DW)
13
17
Up to 129
Comments
Only the 64-bit addressing format is supported.
Only the 64-bit addressing format is supported.
The ICH4 breaks large read requests down in to smaller aligned
read requests based on the setting of the Read Request Max
Length field.
The EHC Asynchronous DMA Engine (ADE) does not generate accesses to main memory unless
all four of the following conditions are met. (Note that the ADE may be active when the periodic
schedule is actively executed, unlike the description in the EHCI specification; since the EHC
contains independent DMA engines, the ADE may perform memory accesses interleaved with the
PDE accesses.)
• The HCHalted bit is 0 (memory space, offset 24h, bit 12). Software clears this bit indirectly by
setting the RUN/STOP bit to 1.
• The Asynchronous Schedule Status bit is 1 (memory space, offset 24h, bit 14). Software sets
this bit indirectly by setting the Asynchronous Schedule Enable Bit to 1.
• The Bus Master Enable bit is 1 (configuration space, offset 04h, bit 2).
• The ADE is not sleeping due to the detection of an empty schedule. There is not one single bit
that indicates this state. However, the sleeping state is entered when the Queue Head with the
H bit set is encountered when the Reclamation bit in the USB EHCI Status register is 0.
198
Intel^® 82801DB ICH4 Datasheet