82801DB Datasheet, PDF (452/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

SMBus Controller Registers (D31:F3)
13.1.3
13.1.4
CMD—Command Register (SMBUS—D31:F3)
Address:
Default Value:
04–05h
0000h
Attributes:
Size:
RO R/W
16 bits
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Description
Reserved
Fast Back to Back Enable (FBE) — RO. Reserved as 0.
SERR# Enable (SERR_EN) — RO. Reserved as 0.
Wait Cycle Control (WCC) — RO. Reserved as 0.
Parity Error Response (PER) — RO. Reserved as 0.
VGA Palette Snoop (VPS) — RO. Reserved as 0.
Postable Memory Write Enable (PMWE) — RO. Reserved as 0.
Special Cycle Enable (SCE) — RO. Reserved as 0.
Bus Master Enable (BME) — RO. Reserved as 0.
Memory Space Enable (MSE) — RO. Reserved as 0.
I/O Space Enable (IOSE) — R/W.
0 = Disable
1 = Enables access to the SM Bus I/O space registers as defined by the Base Address Register.
STA—Device Status Register (SMBUS—D31:F3)
Address:
Default Value:
06–07h
0280h
Attributes:
Size:
RO R/WC
16 bits
Bit
Description
15 Detected Parity Error (DPE) — RO. Reserved as 0.
14 Signaled System Error (SSE) — RO. Reserved as 0.
13 Received Master Abort (RMA) — RO. Reserved as 0.
12 Received Target Abort (RTA) — RO. Reserved as 0.
Signaled Target Abort (STA) — R/WC.
11 _{Set when the function is targeted with a transaction that the ICH4 terminates with a target abort.}
Software resets STA to 0 by writing a 1 to this bit location.
DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field defines the timing for DEVSEL#
10:9 ^{assertion for positive decode.}
01 = Medium timing.
8 Data Parity Error Detected (DPED) — RO. Reserved as 0.
7 Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
6 User Definable Features (UDF) — RO. Reserved as 0.
5 66 MHz Capable (66MHZ_CAP) — RO. Reserved as 0.
4:0 Reserved
452
Intel^® 82801DB ICH4 Datasheet