82801DB Datasheet, PDF (314/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
Bit
Description
D31_F3_Disable — R/W. Software sets this bit to disable the SMBus Host controller function. BIOS
must not enable I/O or memory address space decode, interrupt generation, or any other
3
functionality of functions that are to be disabled.
0 = Enable. SMBus controller is enabled
1 = Disable. SMBus controller is disabled
2 Reserved
D31_F1_Disable — R/W. Software sets this bit to disable the IDE controller function. BIOS must not
enable I/O or memory address space decode, interrupt generation, or any other functionality of
1
functions that are to be disabled.
0 = Enable. IDE controller is enabled
1 = Disable. IDE controller is disabled
SMB_FOR_BIOS — R/W. This bit is used in conjunction with bit 3 in this register.
0 = No effect.
0
1 = Allows the SMBus I/O space to be accessible by software when bit 3 in this register is set. The
PCI configuration space is hidden in this case. Note that if bit 3 is set alone, the decode of both
SMBus PCI configuration and I/O space will be disabled.
NOTES:
1. Software must always disable all functionality within the function before disabling the configuration space.
2. Configuration writes to internal ICH4 USB EHCI (D29:F7) and AC ‘97 (D31:F5, F6) devices when disabled
are illegal and may cause undefined results.
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Intel^® 82801DB ICH4 Datasheet