82801DB Datasheet, PDF (493/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

AC ’97 Modem Controller Registers (D31:F6)
AC ’97 Modem Controller Registers
(D31:F6)
15
15.1 AC ’97 Modem PCI Configuration Space (D31:F6)
Register address locations not shown in Table 15-1 should be treated as Reserved.
Table 15-1. AC ‘97 Modem Controller PCI Configuration Register Address Map
(Modem—D31:F6)
Offset
00–01h
02–03h
04–05h
06–07h
08h
09h
0Ah
0Bh
0Eh
10–13h
14–17h
2C–2Dh
2E–2Fh
34h
3Ch
3Dh
50–51h
52–53h
54–55h
Mnemonic
VID
DID
PCICMD
PCISTA
RID
PI
SCC
BCC
HEDT
MMBAR
MBAR
SVID
SID
CAP_PTR
INTR_LN
INT_PN
PID
PC
PCS
Register
Vendor Identification
Device Identification
PCI Command
PCI Device Status
Revision Identification
Programming Interface
Sub Class Code
Base Class Code
Header Type
Modem Mixer Base Address
Modem Base Address
Subsystem Vendor ID
Subsystem ID
Capabilities Pointer
Interrupt Line
Interrupt Pin
PCI Power Management ID
Power Management Capabilities
Power Management Control and Status
Default
8086
24C6h
0000
0290h
See Note
00
03h
07h
00
00000001h
00000001h
0000h
0000h
50h
00h
02h
0001h
C9C2h
0000h
Access
RO
RO
R/W, RO
R/WC, RO
RO
RO
RO
RO
RO
R/W, RO
R/W, RO
R/WO
R/WO
RO
RO
RO
RO
RO
R/WC, R/W
NOTE: Refer to the ICH4 Specification Update for the value of the Revision ID Register.
Note: Internal reset as a result of D3_HOT to D0 transition will reset all the core well registers except the
following BIOS programmed registers as BIOS may not be invoked following the D3-to-D0
transition. All resume well registers will not be reset by the D3_HOT to D0 transition.
Core Well registers NOT reset by the D3_HOT to D0 transition:
• offset 2Ch–2Dh; Subsystem Vendor ID (SVID)
• offset 2Eh–2Fh; Subsystem ID (SID)
Resume Well registers will not be reset by the D3_HOT to D0 transition:
• offset 54h–55h; Power Management Control and Status (PCS)
Intel^® 82801DB ICH4 Datasheet
493