82801DB Datasheet, PDF (380/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.10.4
GPO_BLINK—GPO Blink Enable Register
Offset Address:
Default Value:
Lockable:
GPIOBASE +18h
0004 0000h
No
Attribute:
Size:
Power Well:
R/W
32-bit
See bit description
Bit
Description
31:29, 26,
24:20, 17:0
28:27, 25
19:18
Reserved
GP_BLINK[n] — R/W. The setting of these bits will have no effect if the corresponding GPIO
is programmed as an input. These bits correspond to GPIO that are in the Resume well, and
will be reset to their default values by RSMRST# or a write to the CF9h register.
0 = The corresponding GPIO will function normally.
1 = If the corresponding GPIO is programmed as an output, the output signal will blink at a
rate of approximately once per second. The high and low times have approximately 0.5
seconds each. The GP_LVL bit is not altered when this bit is set.
GP_BLINK[n] — R/W. The setting of these bits will have no effect if the corresponding GPIO
is programmed as an input. These bits correspond to GPIO that are in the Core well, and will
be reset to their default values by PCIRST#.
0 = The corresponding GPIO will function normally.
1 = If the corresponding GPIO is programmed as an output, the output signal will blink at a
rate of approximately once per second. The high and low times are approximately 0.5
seconds each. The GP_LVL bit is not altered when this bit is set.
NOTE: GPIO[18] will blink by default immediately after reset. This signal could be connected to an LED to
indicate a failed boot (by programming BIOS to clear GP_BLINK[18] after successful POST).
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Intel^® 82801DB ICH4 Datasheet