82801DB Datasheet, PDF (454/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

SMBus Controller Registers (D31:F3)
13.1.9
SVID — Subsystem Vendor ID (SMBUS—D31:F2/F4)
Address Offset:
Default Value:
Lockable:
2Ch–2Dh
00h
No
Attribute:
Size:
Power Well:
RO
16 bits
Core
Bit
Description
Subsystem Vendor ID (SVID) — RO. The SVID register, in combination with the Subsystem ID
15:0
(SID) register, enables the operating system (OS) to distinguish subsystems from each other. The
value returned by reads to this register is the same as that which was written by BIOS into the
IDE_SVID register.
13.1.10
SID — Subsystem ID (SMBUS—D31:F2/F4)
Address Offset:
Default Value:
Lockable:
2Eh–2Fh
00h
No
Attribute:
Size:
Power Well:
RO
16 bits
Core
Bit
Description
Subsystem ID (SID) — R/Write-Once. The SID register, in combination with the SVID register,
15:0 enables the operating system (OS) to distinguish subsystems from each other. The value returned
by reads to this register is the same as that which was written by BIOS into the IDE_SID register.
13.1.11
INTR_LN—Interrupt Line Register (SMBUS—D31:F3)
Address Offset: 3Ch
Default Value: 00h
Attributes:
Size:
R/W
8 bits
Bit
Description
7:0
Interrupt Line (INT_LN) — R/W. This data is not used by the ICH4. It is to communicate to software
the interrupt line that the interrupt pin is connected to PIRQB#.
13.1.12
INTR_PN—Interrupt Pin Register (SMBUS—D31:F3)
Address Offset: 3Dh
Default Value: 02h
Attributes:
Size:
RO
8 bits
Bit
Description
Interrupt Pin (INT_PN) — RO.
7:0
02h = Indicates that the ICH4 SMBus controller will drive PIRQB# as its interrupt line.
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Intel^® 82801DB ICH4 Datasheet