82801DB Datasheet, PDF (124/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
Table 5-26. Interrupt Message Data Format
Bit
31:16
15
14
13:12
11
10:8
7:0
Description
Will always be 0000h.
Trigger Mode: 1 = Level, 0 = Edge. Same as the corresponding bit in the I/O Redirection Table for
that interrupt.
Delivery Status: 1 = Assert, 0 = Deassert.
If using edge-triggered interrupts, then bit will always be 1, since only the assertion is sent.
If using level-triggered interrupts, then this bit indicates the state of the interrupt input.
Will always be 00.
Destination Mode: 1 = Logical. 0 = Physical. Same as the corresponding bit in the I/O Redirection
Table for that interrupt.
Delivery Mode: This is the same as the corresponding bits in the I/O Redirection Table for that
interrupt.
000 = Fixed 100 = NMI
001 = Lowest Priority 101 = INIT
010 = SMI/PMI 110 = Reserved
011 = Reserved 111 = ExtINT
Vector: This is the same as the corresponding bits in the I/O Redirection Table for that interrupt.
5.9
Serial Interrupt (D31:F0)
The ICH4 supports a serial IRQ scheme. This allows a single signal to be used to report interrupt
requests. The signal used to transmit this information is shared between the host, the ICH4, and all
peripherals that support serial interrupts. The signal line, SERIRQ, is synchronous to PCI clock,
and follows the sustained tri-state protocol that is used by all PCI signals. This means that if a
device has driven SERIRQ low, it will first drive it high synchronous to PCI clock and release it the
following PCI clock. The serial IRQ protocol defines this sustained tri-state signaling in the
following fashion:
• S - Sample Phase. Signal driven low
• R - Recovery Phase. Signal driven high
• T - Turn-around Phase. Signal released
The ICH4 supports a message for 21 serial interrupts. These represent the 15 ISA interrupts
(IRQ[0:1, 2:15]), the four PCI interrupts, and the control signals SMI# and IOCHK#. The serial
IRQ protocol does not support the additional APIC interrupts (20–23).
Note: When the IDE primary and secondary controllers are configured for native IDE mode, the only
way to use the internal IRQ14 and IRQ15 connections to the Interrupt controllers is through the
Serial Interrupt pin.
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Intel^® 82801DB ICH4 Datasheet