82801DB Datasheet, PDF (141/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.12.5.2
Transition Rules among S0/Cx and Throttling States
The following priority rules and assumptions apply among the various S0/Cx and throttling states:
• Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This is because
the processor can only perform one register access at a time and Sleep states have higher
priority than thermal throttling.
• When the SLP_EN bit is set (system going to a sleep state (S1–S5), the THTL_EN bit can be
internally treated as being disabled (no throttling while going to sleep state). Note that thermal
throttling (based on THRM# signal) cannot be disabled in an S0 state. However, once the
SLP_EN bit is set, the thermal throttling is shut off (since STPCLK# will be active in S1–S5
states).
• If the THTL_EN bit is set, and a Level 2read then occurs, the system should immediately go
and stay in a C2state until a break event occurs. A Level 2read has higher priority than the
software initiated throttling or thermal throttling.
• If Thermal Override is causing throttling, and a Level 2read then occurs, the system will stay
in a C2 state until a break event occurs. A Level 2read has higher priority than the Thermal
Override.
• After an exit from a C2state (due to a Break event), and if the THTL_EN bit is still set, or if a
Thermal Override is still occurring, the system will continue to throttle STPCLK#. Depending
on the time of break event, the first transition on STPCLK# active can be delayed by up to one
THRM period (1024 PCI clocks=30.72 microseconds).
• The Host controller must post Stop-Grant cycles in such a way that the processor gets an
indication of the end of the special cycle prior to the ICH4 observing the Stop-Grant cycle.
This ensures that the STPCLK# signals stays active for a sufficient period after the processor
observes the response phase.
• If in the C1 state and the STPCLK# signal goes active, the processor will generate a Stop-
Grant cycle, and the system should go to the C2 state. When STPCLK# goes inactive, it should
return to the C1 state.
5.12.6 Sleep States
5.12.6.1
Sleep State Overview
The ICH4 directly supports different sleep states (S1–S5), which are entered by setting the
SLP_EN bit, or due to a Power Button press. The entry to the Sleep states are based on several
assumptions:
• Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because the
processor can only perform one register access at a time. A request to Sleep always has higher
priority than throttling.
• Prior to setting the SLP_EN bit, the software turns off processor-controlled throttling. Note
that thermal throttling cannot be disabled, but setting the SLP_EN bit disables thermal
throttling (since S1–S5 sleep state has higher priority).
• The G3 state cannot be entered via any software mechanism. The G3 state indicates a
complete loss of power.
Intel^® 82801DB ICH4 Datasheet
141