82801DB Datasheet, PDF (6/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

5.2 LAN Controller (B1:D8:F0)............................................................................. 72
5.2.1 LAN Controller Architectural Overview ............................................. 73
5.2.2 LAN Controller PCI Bus Interface ..................................................... 75
5.2.3 Serial EEPROM Interface ................................................................. 83
5.2.4 CSMA/CD Unit.................................................................................. 84
5.2.5 Media Management Interface ........................................................... 85
5.2.6 TCO Functionality ............................................................................. 85
5.3 LPC Bridge (w/ System and Management Functions) (D31:F0).................... 86
5.3.1 LPC Interface .................................................................................... 86
5.4 DMA Operation (D31:F0) ............................................................................... 92
5.4.1 Channel Priority ................................................................................ 93
5.4.2 Address Compatibility Mode ............................................................. 93
5.4.3 Summary of DMA Transfer Sizes ..................................................... 94
5.4.4 Autoinitialize...................................................................................... 94
5.4.5 Software Commands ........................................................................ 95
5.5 PCI DMA........................................................................................................ 96
5.5.1 PCI DMA Expansion Protocol ........................................................... 96
5.5.2 PCI DMA Expansion Cycles ............................................................. 97
5.5.3 DMA Addresses................................................................................ 98
5.5.4 DMA Data Generation ...................................................................... 98
5.5.5 DMA Byte Enable Generation........................................................... 98
5.5.6 DMA Cycle Termination .................................................................... 99
5.5.7 LPC DMA .......................................................................................... 99
5.5.8 Asserting DMA Requests.................................................................. 99
5.5.9 Abandoning DMA Requests ........................................................... 100
5.5.10 General Flow of DMA Transfers ..................................................... 100
5.5.11 Terminal Count ............................................................................... 101
5.5.12 Verify Mode..................................................................................... 101
5.5.13 DMA Request Deassertion ............................................................. 101
5.5.14 SYNC Field / LDRQ# Rules ............................................................ 102
5.6 8254 Timers (D31:F0).................................................................................. 103
5.6.1 Timer Programming ........................................................................ 103
5.6.2 Reading from the Interval Timer ..................................................... 104
5.7 8259 Interrupt Controllers (PIC) (D31:F0) ................................................... 106
5.7.1 Interrupt Handling ........................................................................... 107
5.7.2 Initialization Command Words (ICWx) ............................................ 108
5.7.3 Operation Command Words (OCW) ............................................... 109
5.7.4 Modes of Operation ........................................................................ 109
5.7.5 Masking Interrupts .......................................................................... 112
5.7.6 Steering PCI Interrupts ................................................................... 112
5.8 Advanced Interrupt Controller (APIC) (D31:F0) ........................................... 113
5.8.1 Interrupt Handling ........................................................................... 113
5.8.2 Interrupt Mapping............................................................................ 113
5.8.3 APIC Bus Functional Description.................................................... 114
5.8.4 PCI Message-Based Interrupts....................................................... 121
5.8.5 Processor System Bus Interrupt Delivery ....................................... 122
5.9 Serial Interrupt (D31:F0) .............................................................................. 124
5.9.1 Start Frame..................................................................................... 125
5.9.2 Data Frames ................................................................................... 125
5.9.3 Stop Frame ..................................................................................... 125
5.9.4 Specific Interrupts Not Supported via SERIRQ............................... 126
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Intel^® 82801DB ICH4 Datasheet