82801DB Datasheet, PDF (361/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
Bit
Description
SMBus Wake Status (SMB_WAK_STS) — R/WC. The SMBus controller can independently
cause an SMI# or SCI, so this bit does not need to do so (unlike the other bits in this register).
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware to indicate that the wake event was caused by the ICH4’s SMBus logic.This
bit will be set by the WAKE/SMI# command type, even if the system is already awake. The
SMI handler should then clear this bit.
NOTES:
1. This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the system is in the
7
S0 state. Therefore, to avoid an instant wake on subsequent transitions to sleep states,
software must clear this bit after each reception of the Wake/SMI# command or just prior to
entering the sleep state.
2. If SMB_WAK_STS is set due to SMBus slave receiving a message, it will be cleared by
internal logic when a THRMTRIP# event happens or a Power Button Override event.
However, THRMTRIP# or Power Button Override event will not clear SMB_WAK_STS if it is
set due to SMBALERT# signal going active.
3. The SMBALERT_STS bit (D31:F3:I/O Offset 00h:Bit 5) should be cleared by software before
this bit is cleared.
TCOSCI_STS — R/WC.
6
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the TCO logic causes an SCI.
AC97_STS — R/WC. This bit will be set to 1 by when the codecs are attempting to wake the
system and the PME events for the codecs are armed for wakeup. A PME is armed by
programming the appropriate PMEE bit in the Power Management Control and Status register at
bit 8 of offset 54h in each AC ’97 function.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the codecs are attempting to wake the system. The AC97_STS bit
5
gets set only from the following two cases:
• The PMEE bit for the function is set, and o The AC-link bit clock has been shut and the
routed AC_SDIN line is high (for audio, if routing is disabled, no wake events are
allowed.
• For modem, if audio routing is disabled, then the wake event is an OR of all AC_SDIN
lines. If routing is enabled, then the wake event for modem is the remaining non-routed
AC_SDIN line), or o GPI Status Change Interrupt bit (NABMBAR + 30h, bit 0) is 1.
This bit is not affected by a hard reset caused by a CF9h write.
USB2_STS — R/WC.
4
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when USB UHCI controller 2 needs to cause a wake. Wake event will be
generated if the corresponding USB2_EN bit is set.
USB1_STS — R/WC.
3
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when USB UHCI controller 1 needs to cause a wake. Wake event will be
generated if the corresponding USB1_EN bit is set.
2
Reserved
Thermal Interrupt Override Status (THRMOR_STS) — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1
1 = This bit is set by hardware anytime a thermal over-ride condition occurs and starts throttling
the processor’s clock at the THRM_DTY ratio. This will not cause an SMI#, SCI, or wake
event.
Thermal Interrupt Status (THRM_STS) — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
0
1 = Set by hardware anytime the THRM# signal is driven active as defined by the THRM_POL
bit. Additionally, if the THRM_EN bit is set, then the setting of the THRM_STS bit will also
generate a power management event (SCI or SMI#).
Intel^® 82801DB ICH4 Datasheet
361