82801DB Datasheet, PDF (54/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Signal Description
2.20.2 External RTC Circuitry
To reduce RTC well power consumption, the ICH4 implements an internal oscillator circuit that is
sensitive to step voltage changes in VccRTC and VBIAS. Figure 2-2 shows a schematic diagram of
the circuitry required to condition these voltages to ensure correct operation of the ICH4 RTC.
Figure 2-2. Example External RTC Circuit
3.3 V
VccSus
1 µF
VccRTC
1 kΩ
Vbatt
32.768 kHz
Xtal
C3
0.047 uF
C1
18 pF
C2
18 pF
NOTES:
1. Reference designators arbitrarily assigned.
2. 3.3 V VccSus is active when system plugged in.
3. Vbatt is voltage provided by battery.
4. VBIAS, VccRTC, RTCX1, and RTCX2 are Intel^® ICH4 pins.
5. VBIAS is used to bias the ICH4 internal oscillator.
6. VccRTC powers the RTC well of the ICH4.
7. RTCX1 is the input to the internal oscillator.
8. RTCX2 is the feedback for the external crystal.
9. C1 and C2 depend on crystal load.
RTCX2
R1
10 MΩ
RTCX1
R2
10 MΩ
VBIAS
RTC_osc_circ
2.20.3
V5REF / Vcc3_3 Sequencing Requirements
V5REF is the reference voltage for 5 V tolerance on inputs to the ICH4. V5REF must be powered
up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or
before Vcc3_3 within 0.7 V. The rule must be followed in order to ensure the safety of the ICH4. If
the rule is violated, internal diodes will attempt to draw power sufficient to damage the diodes from
the Vcc3_3 rail. Figure 2-3 shows a sample implementation of how to satisfy the V5REF/3.3 V
sequencing rule.
This rule also applies to the standby rails, but in most platforms, the VccSus3_3 rail is derived from
the VccSus5 rail and therefore, the VccSus3_3 rail will always come up after the VccSus5 rail. As
a result, V5REF_Sus will always be powered up before VccSus3_3. In platforms that do not derive
the VccSus3_3 rail from the VccSus5 rail, this rule must be comprehended in the platform design.
54
Intel^® 82801DB ICH4 Datasheet