82801DB Datasheet, PDF (146/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.12.7.4
5.12.7.5
Processor-Initiated Passive Cooling (Via Programmed Duty Cycle on
STPCLK#)
Using the THTL_EN and THTL_DTY bits, the ICH4 can force a programmed duty cycle on the
STPCLK# signal. This reduces the effective instruction rate of the processor and cut its power
consumption and heat generation.
Active Cooling
Active cooling involves fans. The GPIO signals from the ICH4 can be used to turn on/off a fan.
5.12.8 Event Input Signals and Their Usage
The ICH4 has various input signals that trigger specific events. This section describes those signals
and how they should be used.
5.12.8.1
PWRBTN# - Power Button
The ICH4 PWRBTN# signal operates as a “Fixed Power Button” as described in the ACPI
specification. PWRBTN# signal has a 16 ms de-bounce on the input. The state transition
descriptions are included in Table 5-44. Note that the transitions start as soon as the PWRBTN# is
pressed (but after the debounce logic), and does not depend on when the Power Button is released.
Table 5-44. Transitions Due to Power Button
Present
State
S0/Cx
S1–S5
G3
S0–S4
Event
Transition/Action
Comment
PWRBTN# goes low
PWRBTN# goes low
PWRBTN# pressed
PWRBTN# held low for
at least 4 consecutive
seconds
SMI# or SCI generated
(depending on SCI_EN)
Wake Event. Transitions to
S0 state.
None
Unconditional transition to S5
state.
Software will typically initiate a
Sleep state.
Standard wakeup
No effect since no power.
Not latched nor detected.
No dependence on processor
(e.g., Stop-Grant cycles) or any
other subsystem.
Power Button Override Function
If PWRBTN# is observed active for at least four consecutive seconds, then the state machine
should unconditionally transition to the G2/S5 state, regardless of present state (S0–S4). In this
case, the transition to the G2/S5 state should not depend on any particular response from the
processor (e.g., a Stop-Grant cycle), nor any similar dependency from any other subsystem.
New: A power button override will force a transition to S5, even if PWROK is not active.
The PWRBTN# status is readable to check if the button is currently being pressed or has been
released. The status is taken after the de-bounce, and is readable via the PWRBTN_LVL bit.
Note:
The 4-second PWRBTN# assertion should only be used if a system lock-up has occurred. The
4-second timer starts counting when the ICH4 is in a S0 state. If the PWRBTN# signal is asserted
and held active when the system is in a suspend state (S1–S5), the assertion causes a wake event.
Once the system has resumed to the S0 state, the 4-second timer starts.
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Intel^® 82801DB ICH4 Datasheet