82801DB Datasheet, PDF (303/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
Bit
Description
APIC Enable (APIC_EN) — R/W.
0 = Disables internal I/O (x) APIC.
1 = Enables the internal I/O (x) APIC and its address decode.
The following behavioral rules apply for bits 8 and 7 in this register:
• Rule 1: If bit 8 is 0, the ICH4 does not decode any of the registers associated with the I/O APIC
or I/O (x) APIC. The state of bit 7 is “Don’t Care” in this case.
8
• Rule 2: If bit 8 is 1 and bit 7 is 0, the ICH4 decodes the memory space associated with the I/O
APIC, but not the extra registers associated I/O (x) APIC.
• Rule 3: If bit 8 is 1 and bit 7 is 1, the ICH4 decodes the memory space associated with both the
I/O APIC and the I/O (x) APIC. This also enables PCI masters to write directly to the register to
cause interrupts (PCI Message Interrupt).
NOTE: There is no separate way to disable PCI Message Interrupts if the I/O (x) APIC is enabled.
This is not considered necessary.
I/O (x) Extension Enable (XAPIC_EN) — R/W.
0 = The I/O (x) APIC extensions are not supported.
7 _{1 = Enables the extra features (beyond standard I/O APIC) associated with the I/O (x) APIC.}
NOTE: This bit is only valid if the APIC_EN bit is also set to 1.
Alternate Access Mode Enable (ALTACC_EN) — R/W.
6
0 = Alt Access Mode Disabled (default). ALT access mode allows reads to otherwise unreadable
registers and writes otherwise unwritable registers.
1 = Alt Access Mode Enable.
5:4 Reserved
3 Reserved — RO. Reset 0.
DMA Collection Buffer Enable (DCB_EN) — R/W.
2 0 = DCB disabled.
1 = Enables DMA Collection Buffer (DCB) for LPC I/F and PC/PCI DMA.
Delayed Transaction Enable (DTE) — R/W.
1 0 = Delayed transactions disabled.
1 = ICH4 enables delayed transactions for internal register, FWH and LPC I/F accesses.
Positive Decode Enable (POS_DEC_EN) — R/W.
0 = The ICH4 will perform subtractive decode on the PCI bus and forward the cycles to LPC I/F if
0
not to an internal register or other known target on the LPC I/F. Accesses to internal registers
and to known LPC I/F devices will still be positively decoded.
1 = Enables ICH4 to only perform positive decode on the PCI bus.
Intel^® 82801DB ICH4 Datasheet
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