82801DB Datasheet, PDF (363/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.8.3.9
Bit
Description
USB1_EN — R/W.
0 = Disable.
3
1 = Enable the setting of the USB1_STS bit to generate a wake event. The USB1_STS bit is set
anytime USB UHCI controller #1 signals a wake event. Break events are handled via the
USB interrupt.
THRM#_POL — R/W. This bit controls the polarity of the THRM# pin needed to set the
THRM_STS bit.
2
0 = Low value on the THRM# signal will set the THRM_STS bit.
1 = HIGH value on the THRM# signal will set the THRM_STS bit.
1
Reserved
THRM_EN — R/W.
0
0 = Disable.
1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set the
THRM_STS bit and generate a power management event (SCI or SMI).
SMI_EN—SMI Control and Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 30h
0000h
No
Core
Attribute:
Size:
Usage:
R/W, WO, R/W-Special
32 bit
ACPI or Legacy
Bit
Description
31:19
18
17
16:15
14
13
12
11
10:8
Reserved
INTEL_USB2_EN — R/W.
0 = Disable.
1 = Enables Intel-Specific USB EHCI SMI logic to cause SMI#.
LEGACY_USB2_EN — R/W.
0 = Disable.
1 = Enables legacy USB EHCI logic to cause SMI#.
Reserved
PERIODIC_EN — R/W.
0 = Disable.
1 = Enables the Intel^® ICH4 to generate an SMI# when the PERIODIC_STS bit is set in the
SMI_STS register.
TCO_EN — R/W.
0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is set, SMIs that are
caused by re-routed NMIs will not be gated by the TCO_EN bit. Even if the TCO_EN bit is 0,
NMIs will still be routed to cause SMIs.
1 = Enables the TCO logic to generate SMI#.
Reserved
Microcontroller SMI Enable (MCSMI_EN) — R/W.
0 = Disable.
1 = Enables ICH4 to trap accesses to the microcontroller range (62h or 66h) and generate an
SMI#. Note that “trapped’ cycles will be claimed by the ICH4 on PCI, but not forwarded to LPC.
Reserved
Intel^® 82801DB ICH4 Datasheet
363