82801DB Datasheet, PDF (464/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

SMBus Controller Registers (D31:F3)
13.2.16 SLV_CMD—Slave Command Register
Register Offset: 11h
Default Value: 00h
Attribute:
Size:
Note: This register is in the resume well and is reset by RSMRST#
R/W
8 bits
Bit
Description
7:2 Reserved
SMBALERT_DIS — R/W.
0 = Allows the generation of the interrupt or SMI#.
2 ^{1 = Software sets this bit to block the generation of the interrupt or SMI# due to the SMBALERT#}
source. This bit is logically inverted and ANDed with the SMBALERT_STS bit. The resulting
signal is distributed to the SMI# and/or interrupt generation logic. This bit does not effect the
wake logic.
HOST_NOTIFY_WKEN — R/W.
0 = Disable.
1 _{1 = Enables the reception of a Host Notify command as a wake event. When enabled this event is}
“OR”ed in with the other SMBus wake events and is reflected in the SMB_WAK_STS bit of the
General Purpose Event 0 Status register.
HOST_NOTIFY_INTREN — R/W.
0 = Disable
1 = Enables the generation of interrupt or SMI# when HOST_NOTIFY_STS is 1. This enable does
0
not affect the setting of the HOST_NOTIFY_STS bit. When the interrupt is generated, either
PIRQ[B]# or SMI# is generated, depending on the value of the SMB_SMI_EN bit (D31, F3,
Off40h, B1). If the HOST_NOTIFY_STS bit is set when this bit is written to a 1, then the interrupt
(or SMI#) will be generated. The interrupt (or SMI#) is logically generated by AND’ing the STS
and INTREN bits.
13.2.17 NOTIFY_DADDR—Notify Device Address
Register Offset: 14h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Note: This register is in the resume well and is reset by RSMRST#
Bit
Description
DEVICE_ADDRESS — RO. This field contains the 7-bit device address received during the Host
7:1 Notify protocol of the SMBus 2.0 Specification. Software should only consider this field valid when the
HOST_NOTIFY_STS bit is set to 1.
0 Reserved
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Intel^® 82801DB ICH4 Datasheet