82801DB Datasheet, PDF (240/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.19.6 System Reset
Table 5-103 indicates the states of the link during various system reset and sleep conditions.
Table 5-103. AC-link State during PCIRST#
Signal
Power
Plane
I/O
During
PCIRST#/
AC_RST#
Resume³ Output
Low
AC_SDOUT Core¹
AC_SYNC
Core
AC_BIT_CLK Core
AC_SDIN[2:0] Resume
Output
Output
Input
Input
Low
Low
Driven by codec
Driven by codec
After
PCIRST#/
Low
Running
Running
Running
Running
S1
Cold Reset
bit (Hi)
Low
Low
Low^2,4
Low^2,4
S3
Low
Low
Low
Low^2,4
Low^2,4
S4/S5
Low
Low
Low
Low^2,4
Low^2,4
NOTES:
1. ICH4 core well outputs are used as strapping options for the ICH4, sampled during system reset. These
signals may have weak pullups/pulldowns on them. The ICH4 outputs will be driven to the appropriate level
prior to AC_RST# being deasserted, preventing a codec from entering test mode. Straps are tied to the core
well to prevent leakage during a suspend state.
2. The pull-down resistors on these signals are only enabled when the AC-Link Shut Off bit in the AC ’97 Global
Control Register is set to 1. All other times, the pull-down resistor is disabled.
3. AC_RST# will be held low during S3–S5. It cannot be programmed high during a suspend state.
4. AC_BIT_CLK and AC_SDIN[2:0] are driven low by the codecs during normal states. If the codec is powered
during suspend states it will hold these signals low. However, if the codec is not present, or not powered in
suspend, external pull-down resistors are required.
The transition of AC_RST# to the deasserted state will only occur under driver control. In the
S1sleep state, the state of the AC_RST# signal is controlled by the AC ’97 Cold Reset# bit (bit 1)
in the Global Control register. AC_RST# will be asserted (low) by the ICH4 under the following
conditions:
• RSMRST# (system reset, including the a reset of the resume well and PCIRST#)
• Mechanical power up (causes PCIRST#)
• Write to CF9h hard reset (causes PCIRST#)
• Transition to S3/S4/S5 sleep states (causes PCIRST#)
• Write to AC ’97 Cold Reset# bit in the Global Control Register.
Hardware will never deassert AC_RST# (i.e., never deasserts the Cold Reset# bit) automatically.
Only software can deassert the Cold Reset# bit, and hence the AC_RST# signal. This bit, while it
resides in the core well, will remain cleared upon return from S3/S4/S5 sleep states. The AC_RST#
pin will remain actively driven from the resume well as indicated.
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Intel^® 82801DB ICH4 Datasheet