82801DB Datasheet, PDF (191/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.16.6.2
Data Buffer Error
This event indicates that an overrun of incoming data or a under-run of outgoing data has occurred
for this transaction. This would generally be caused by the ICH4 not being able to access required
data buffers in memory within necessary latency requirements. Either of these conditions will
cause the C_ERR field of the TD to be decremented.
When C_ERR decrements to zero, the Active bit in the TD is cleared, the Stalled bit is set, the USB
Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a hardware
interrupt is signaled to the system.
Bit Stuff Error
A bit stuff error results from the detection of a sequence of more than 6 ones in a row within the
incoming data stream. This will cause the C_ERR field of the TD to be decremented. When the
C_ERR field decrements to zero, the Active bit in the TD is cleared to 0, the Stalled bit is set to 1,
the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a
hardware interrupt is signaled to the system.
Non-Transaction Based Interrupts
If an ICH4 process error or system error occur, the ICH4 halts and immediately issues a hardware
interrupt to the system.
Resume Received
This event indicates that the ICH4 received a RESUME signal from a device on the USB bus
during a global suspend. If this interrupt is enabled in the Interrupt Enable register, a hardware
interrupt will be signaled to the system allowing the USB to be brought out of the suspend state and
returned to normal operation.
Intel^® ICH4 Process Error
The HC monitors certain critical fields during operation to ensure that it does not process corrupted
data structures. These include checking for a valid PID and verifying that the MaxLength field is
less than 1280. If it detects a condition that would indicate that it is processing corrupted data
structures, it immediately halts processing, sets the HC Process Error bit in the HC Status register
and signals a hardware interrupt to the system.
This interrupt cannot be disabled through the Interrupt Enable register.
Host System Error
The ICH4 sets this bit to 1 when a PCI Parity error, PCI Master Abort, or PCI Target Abort occur.
When this error occurs, the ICH4 clears the Run/Stop bit in the Command register to prevent
further execution of the scheduled TDs. This interrupt cannot be disabled through the Interrupt
Enable register.
Intel^® 82801DB ICH4 Datasheet
191