82801DB Datasheet, PDF (113/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.8
Advanced Interrupt Controller (APIC) (D31:F0)
In addition to the standard ISA-compatible Programmable Interrupt Controller (PIC) described in
Section 5.7, the ICH4 incorporates the Advanced Programmable Interrupt Controller (APIC).
While the standard interrupt controller is intended for use in a uni-processor system, APIC can be
used in either a uni-processor or multi-processor system.
5.8.1
Interrupt Handling
The I/O APIC handles interrupts very differently than the 8259. Briefly, these differences are:
• Method of Interrupt Transmission. The I/O APIC transmits interrupts through a three wire
bus, and interrupts are handled without the need for the processor to run an interrupt
acknowledge cycle.
• Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the interrupt
number. For example, interrupt 10 can be given a higher priority than interrupt 3.
• More Interrupts. The I/O APIC in the ICH4 supports a total of 24 interrupts.
• Multiple Interrupt Controllers. The I/O APIC interrupt transmission protocol has an
arbitration phase, which allows for multiple I/O APICs in the system with their own interrupt
vectors. The ICH4 I/O APIC must arbitrate for the APIC bus before transmitting its interrupt
message.
5.8.2 Interrupt Mapping
The I/O APIC within the ICH4 supports 24 APIC interrupts. Each interrupt has its own unique
vector assigned by software. The interrupt vectors are mapped as follows, and match “Config 6” of
the Multi-Processor Specification.
Table 5-17. APIC Interrupt Mapping (Sheet 1 of 2)
IRQ #
0
1
2
3
4
5
6
7
8
9
10
11
12
Via
SERIRQ
No
Yes
No
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Direct from
pin
No
No
No
No
No
No
No
No
No
No
No
No
No
Via PCI
message
No
Yes
No
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Internal Modules
Cascade from 8259 #1
8254 Counter 0
RTC
Option for SCI, TCO
Option for SCI, TCO
Option for SCI, TCO
Intel^® 82801DB ICH4 Datasheet
113