82801DB Datasheet, PDF (348/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.8.1.3
GEN_PMCON_3—General PM Configuration 3 Register (PM—D31:F0)
Offset Address: A4h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
R/W, R/WC
8 bit
ACPI, Legacy
RTC
Bit
Description
SWSMI_RATE_SEL — R/W. This 2-bit value indicates when the SWSMI timer will time out. Valid
values are:
00 = 1.5 ms ± 0.5 ms
7:6
01 = 16 ms ± 4 ms
10 = 32 ms ± 4 ms
11 = 64 ms ± 4 ms
5:3 Reserved
RTC Power Status (RTC_PWR_STS) — R/W. This bit is set when RTCRST# is low. The bit is not
cleared by any type of reset. When the system boots, BIOS can detect that the FREQ_STRAP
2 register contents are 1111 (the default when RTCRST# has been low). If this bit is also set, then
BIOS knows the RTC battery had been removed. In that case, BIOS should take steps to reprogram
the FREQ_STRAP register with the correct value, and then reboot the system.
Power Failure (PWR_FLR) — R/WC. This bit is in the RTC well, and is not cleared by any type of
reset except RTCRST#.
0 = Indicates that the trickle current has not failed since the last time the bit was cleared. Software
clears this bit by writing a 1 to the bit position.
1 _{1 = Indicates that the trickle current (from the main battery or trickle supply) was removed or failed.}
NOTE: Clearing CMOS in an Intel^® ICH4-based platform can be done by using a jumper on
RTCRST# or GPI, or using SAFEMODE strap. Implementations should not attempt to clear
CMOS by using a jumper to pull VccRTC low.
AFTERG3_EN — R/W. Determines what state to go to when power is re-applied after a power
failure (G3 state). This bit is in the RTC well and is not cleared by any type of reset except writes to
CF9h or RTCRST#.
0 0 = System will return to S0 state (boot) after power is re-applied.
1 = System will return to the S5 state (except if it was in S4, in which case it will return to S4). In the
S5 state, the only enabled wake event is the Power Button or any enabled wake event that was
preserved through the power failure.
NOTE: RSMRST# is sampled using the RTC clock. Therefore, low times that are less than one RTC clock
period may not be detected by the ICH4.
348
Intel^® 82801DB ICH4 Datasheet