82801DB Datasheet, PDF (139/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
Table 5-38. Causes of SMI# and SCI (Sheet 2 of 2)
Cause
SCI SMI
Device monitors match address in
its range
No
Yes
SMBus Host controller
No Yes
SMBus Slave SMI message
No Yes
SMBus SMBALERT# signal active No Yes
SMBus Host Notify message
received
No Yes
Access microcontroller 62h/66h
No Yes
SLP_EN bit written to 1
No Yes
Additional Enables
DEV[n]_TRAP_EN=1
SMB_SMI_EN
Host Controller Enabled
none
none
HOST_NOTIFY_INTREN
MCSMI_EN
SMI_ON_SLP_EN=1
Where Reported
DEVMON_STS,
DEV[n]_TRAP_STS
SMBus host status reg.
SMBUS_SMI_STS
SMBUS_SMI_STS
SMBUS_SMI_STS
HOST_NOTIFY_STS
MCSMI_STS
SMI_ON_SLP_EN_STS
NOTES:
1. SCI_EN must be 1 to enable SCI. SCI_EN must be 0 to enable SMI.
2. SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).
3. GBL_SMI_EN must be 1 to enable SMI.
4. EOS must be written to 1 to re-enable SMI for the next one.
5.12.5 Dynamic Processor Clock Control
The ICH4 has extensive control for dynamically starting and stopping system clocks. The clock
control is used for transitions among the various S0/Cx states, and processor throttling. Each
dynamic clock control method is described in this section. The various Sleep states may also
perform types of non-dynamic clock control.
The ICH4 supports the ACPI C0, C1, and C2 states.
The Dynamic processor clock control is handled using the following signals:
• STPCLK#: Used to halt processor instruction stream.
The C1 state is entered based on the processor performing an auto halt instruction. The C2 state is
entered based on the processor reading the Level 2 register in the ICH4.
A C1, C2 state ends due to a Break event. Based on the break event, the ICH4 returns the system to
C0 state. Table 5-39 lists the possible break events from C2 . The break events from C1 are
indicated in the processor’s datasheet.
Table 5-39. Break Events
Event
Any unmasked interrupt goes active
Any internal event that will cause an
NMI or SMI#
Any internal event that will cause
INIT# to go active
Processor Pending Break Event
Indication
Breaks from
C2
C2
C2
C2
Comment
IRQ[0:15] when using the 8259s, IRQ[0:23] for
I/O APIC. Since SCI is an interrupt, any SCI will
also be a break event.
Many possible sources
Could be indicated by the keyboard controller
via the RCIN input signal.
Only available if FERR# enabled for break event
indication (See GEN_CNTL.FERR# Mux-En bit
in Section 9.1.22).
Intel^® 82801DB ICH4 Datasheet
139