82801DB Datasheet, PDF (319/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.2.7
9.2.8
DMACH_MODE—DMA Channel Mode Register
I/O Address:
Default Value:
Lockable:
Ch. #0–3 = 0Bh;
Ch. #4–7 = D6h
0000 00xx
No
Attribute:
Size:
Power Well:
WO
8 bit
Core
Bit
Description
DMA Transfer Mode — WO. Each DMA channel can be programmed in one of four different modes:
00 = Demand mode
7:6 01 = Single mode
10 = Reserved
11 = Cascade mode
Address Increment/Decrement Select — WO. This bit controls address increment/decrement
during DMA transfers.
5 _{0 = Address increment. (default after part reset or Master Clear)}
1 = Address decrement.
Autoinitialize Enable — WO.
0 = Autoinitialize feature is disabled and DMA transfers terminate on a terminal count. A part reset or
4
Master Clear disables autoinitialization.
1 = DMA restores the Base Address and Count registers to the current registers following a terminal
count (TC).
DMA Transfer Type — WO. These bits represent the direction of the DMA transfer. When the
channel is programmed for cascade mode, (bits[7:6] = 11) the transfer type is irrelevant.
00 = Verify: No I/O or memory strobes generated
3:2 _{01 = Write: Data transferred from the I/O devices to memory}
10 = Read: Data transferred from memory to the I/O device
11 = Illegal
DMA Channel Select — WO. These bits select the DMA Channel Mode Register that will be written
by bits [7:2].
00 = Channel 0 (4)
1:0 _{01 = Channel 1 (5)}
10 = Channel 2 (6)
11 = Channel 3 (7)
DMA Clear Byte Pointer Register
I/O Address:
Default Value:
Lockable:
Ch. #0–3 = 0Ch;
Ch. #4–7 = D8h
xxxx xxxx
No
Attribute:
Size:
Power Well:
WO
8 bit
Core
Bit
Description
Clear Byte Pointer — WO. No specific pattern. Command enabled with a write to the I/O port
address. Writing to this register initializes the byte pointer flip/flop to a known state. It clears the
internal latch used to address the upper or lower byte of the 16-bit Address and Word Count
7:0 Registers. The latch is also cleared by part reset and by the Master Clear command. This command
precedes the first access to a 16-bit DMA controller register. The first access to a 16-bit register will
then access the significant byte, and the second access automatically accesses the most significant
byte.
Intel^® 82801DB ICH4 Datasheet
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