82801DB Datasheet, PDF (565/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Register Index
Table A-1. Intel^® ICH4 PCI Configuration Registers (Sheet 5 of 10)
Register Name
Offset
Datasheet Location
FWH Select 2 Register
EE–EFh
Section 9.1.34, “FWH_SEL2—FWH Select 2 Register (LPC I/F—D31:F0)”
on page 9-311
FWH Decode Enable 2 Register
F0h
Section 9.1.35, “FWH_DEC_EN2—FWH Decode Enable 2 Register (LPC
I/F—D31:F0)” on page 9-312
Function Disable Register
F2h
Section 9.1.36, “FUNC_DIS—Function Disable Register (LPC I/F—
D31:F0)” on page 9-313
General Power Management
Configuration 1
A0h
Section 9.8.1.1, “GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0)” on page 9-346
General Power Management
Configuration 2
A2h
Section 9.8.1.2, “GEN_PMCON_2—General PM Configuration 2 Register
(PM—D31:F0)” on page 9-347
General Power Management
Configuration 3
A4h
Section 9.8.1.3, “GEN_PMCON_3—General PM Configuration 3 Register
(PM—D31:F0)” on page 9-348
Stop Clock Delay Register
A8h
Section 9.8.1.4, “STPCLK_DEL—Stop Clock Delay Register (PM—
D31:F0)” on page 9-349
GPI_ROUT
B8–BBh
Section 9.8.1.5, “GPI_ROUT—GPI Routing Control Register (PM—
D31:F0)” on page 9-349
I/O Monitor Trap Forwarding Enable
Register
C0h
Section 9.8.1.6, “TRP_FWD_EN—IO Monitor Trap Forwarding Enable
Register (PM—D31:F0)” on page 9-350
I/O Monitor [4:7] Trap Range Registers
C4h, C6h,
C8h, CAh
Section 9.8.1.7, “MON[n]_TRP_RNG—I/O Monitor [4:7] Trap Range
Register for Devices 4–7 (PM—D31:F0)” on page 9-351
I/O Monitor [4:7] Trap Mask Register
CCh
Section 9.8.1.8, “MON_TRP_MSK—I/O Monitor Trap Range Mask
Register for Devices 4–7 (PM—D31:F0)” on page 9-351
IDE Controller (D31:F1)
Vendor ID
Device ID
Command Register
Device Status
Revision ID Register
Programming Interface
Sub Class Code
Base Class Code
Master Latency Timer
Primary Command Block Base
Address Register
Primary Contol Block Base Address
Register
Secondary Command Block Base
Address Register
00h–01h
02h–03h
04h–05h
06h–07h
08h
09h
0Ah
0Bh
0Dh
10–13h
14–17h
18–1Bh
Section 10.1.1, “VID—Vendor ID Register (LPC I/F—D31:F1)” on
page 10-384
Section 10.1.2, “DID—Device ID Register (LPC I/F—D31:F1)” on
page 10-384
Section 10.1.3, “CMD — Command Register (IDE—D31:F1)” on
page 10-384
Section 10.1.4, “STS — Device Status Register (IDE—D31:F1)” on
page 10-385
Section 10.1.5, “REVID—Revision ID Register (IDE—D31:F1)” on
page 10-385
Section 10.1.6, “PI — Programming Interface Register (IDE—D31:F1)” on
page 10-386
Section 10.1.7, “SCC — Sub Class Code Register (IDE—D31:F1)” on
page 10-386
Section 10.1.8, “BCC — Base Class Code Register (IDE—D31:F1)” on
page 10-386
Section 10.1.9, “MLT — Master Latency Timer Register (IDE—D31:F1)”
on page 10-387
Section 10.1.10, “PCMD_BAR—Primary Command Block Base Address
Register (IDE—D31:F1)” on page 10-387
Section 10.1.11, “PCNL_BAR—Primary Control Block Base Address
Register (IDE—D31:F1)” on page 10-387
Section 10.1.12, “SCMD_BAR—Secondary Command Block Base
Address Register (IDE D31:F1)” on page 10-388
Intel^® 82801DB ICH4 Datasheet
565