82801DB Datasheet, PDF (162/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.15.1 PIO Transfers
The ICH4 IDE controller includes both compatible and fast timing modes. The fast timing modes
can be enabled only for the IDE data ports. All other transactions to the IDE registers are run in
single transaction mode with compatible timings.
Up to two IDE devices may be attached per IDE connector (drive 0 and drive 1). The IDETIM and
SIDETIM Registers permit different timing modes to be programmed for drive 0 and drive 1 of the
same connector.
The Ultra ATA/33/66/100 synchronous DMA timing modes can also be applied to each drive by
programming the IDE I/O Configuration register and the Synchronous DMA Control and Timing
registers. When a drive is enabled for synchronous DMA mode operation, the DMA transfers are
executed with the synchronous DMA timings. The PIO transfers are executed using compatible
timings or fast timings if also enabled.
5.15.1.1
IDE Port Decode
The Command and Control Block registers are accessed differently depending on the decode
mode, which is selected by the Programming Interface configuration register (Offset 09h).
Note: The primary and secondary channels are controlled by separate bits, allowing one to be in native
mode and the other in legacy mode simultaneously.
5.15.1.2
IDE Legacy Mode and Native Mode
The ICH4 IDE controller supports both legacy mode and PCI native mode. In legacy mode, the
Command and Control Block registers are accessible at fixed I/O addresses. While in legacy mode,
the ICH4 does not decode any of the native mode ranges. Likewise, in native mode the ICH4 does
not decode any of the legacy mode ranges.
The IDE I/O ports involved in PIO transfers are decoded by the ICH4 to the IDE interface when
D31:F1 I/O space is enabled and IDE decode is enabled through the IDE_TIMx registers. The IDE
registers are implemented in the drive itself. An access to the IDE registers results in the assertion
of the appropriate IDE chip select for the register, and the IDE command strobes (PDIOR#/
SDIOR#, PDIOW#/SDIOW#).
There are two I/O ranges for each IDE cable: the Command Block, which corresponds to the
PCS1#/SCS1# chip select, and the Control Block, which corresponds to the PCS3#/SCS3# chip
select. The Command Block is an 8-byte range, while the control block is a 4-byte range.
— Command Block Offset: 01F0h for primary, 0170h for secondary
— Control Block Offset: 03F4h for primary, 0374h for secondary
Table 5-52 and Table 5-53 specify the registers as they affect the ICH4 hardware definition.
Note: The Data Register (I/O Offset 00h) should be accessed using 16-bit or 32-bit I/O instructions. All
other registers should be accessed using 8-bit I/O instructions.
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Intel^® 82801DB ICH4 Datasheet