82801DB Datasheet, PDF (307/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.1.29
FWH_DEC_EN1—FWH Decode Enable 1 Register
(LPC I/F—D31:F0)
Offset Address: E3h
Default Value: FFh
Attribute:
Size:
R/W
8 bits
This register determines which memory ranges will be decoded on the PCI bus and forwarded to
the FWH. The ICH4 will subtractively decode cycles on PCI unless POS_DEC_EN is set to 1.
Bit
Description
FWH_F8_EN — R/W. Enables decoding two 512 KB FWH memory ranges, and one 128KB
memory range.
0 = Disable
7
1 = Enable the following ranges for the FWH
FFF80000h–FFFFFFFFh
FFB80000h–FFBFFFFFh
000E0000h–000FFFFFh
FWH_F0_EN — R/W. Enables decoding two 512 KB FWH memory ranges.
0 = Disable.
6
1 = Enable the following ranges for the FWH:
FFF00000h–FFF7FFFFh
FFB00000h–FFB7FFFFh
FWH_E8_EN — R/W. Enables decoding two 512 KB FWH memory ranges.
0 = Disable.
5
1 = Enable the following ranges for the FWH:
FFE80000h–FFEFFFFh
FFA80000h–FFAFFFFFh
FWH_E0_EN — R/W. Enables decoding two 512 KB FWH memory ranges.
0 = Disable.
4
1 = Enable the following ranges for the FWH:
FFE00000h–FFE7FFFFh
FFA00000h–FFA7FFFFh
FWH_D8_EN — R/W. Enables decoding two 512 KB FWH memory ranges.
0 = Disable.
3
1 = Enable the following ranges for the FWH
FFD80000h–FFDFFFFFh
FF980000h–FF9FFFFFh
FWH_D0_EN — R/W. Enables decoding two 512KB FWH memory ranges.
0 = Disable.
2
1 = Enable the following ranges for the FWH
FFD00000h–FFD7FFFFh
FF900000h–FF97FFFFh
FWH_C8_EN — R/W. Enables decoding two 512KB FWH memory ranges.
0 = Disable.
1
1 = Enable the following ranges for the FWH
FFC80000h–FFCFFFFFh
FF880000h–FF8FFFFFh
FWH_C0_EN — R/W. Enables decoding two 512 KB FWH memory ranges.
0 = Disable.
0
1 = Enable the following ranges for the FWH
FFC00000h–FFC7FFFFh
FF800000h–FF87FFFFh
Intel^® 82801DB ICH4 Datasheet
307