82801DB Datasheet, PDF (390/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

IDE Controller Registers (D31:F1)
10.1.18
INTR_LN—Interrupt Line Register (IDE—D31:F1)
Address Offset: 3Ch
Default Value: 00h
Attribute: R/W
Size:
8 bits
Bit
Description
7:0
Interrupt Line (INT_LN) — R/W. It is to communicate to software the interrupt line that the
interrupt pin is connected to.
10.1.19
INTR_PN—Interrupt Pin Register (IDE—D31:F1)
Address Offset: 3Dh
Default Value: 01h
Attribute: RO
Size:
8 bits
Bit
Description
7:3 Reserved
Interrupt Pin (INT_PN) — RO. The value of 01h indicates to “software” that the ICH4 will drive
2:0
INTA#. Note that this is only used in native mode. Also note that the routing to the internal interrupt
controller does not necessarily relate to the value in this register. The IDE interrupt is in fact routed
to PIRQ[C]# (IRQ18 in APIC mode).
10.1.20
IDE_TIM — IDE Timing Register (IDE—D31:F1)
Address Offset:
Default Value:
Primary: 40–41h
Secondary: 42–43h
0000h
Attribute: R/W
Size:
16 bits
This register controls the timings driven on the IDE cable for PIO and 8237 style DMA transfers. It
also controls operation of the buffer for PIO transfers.
Bit
Description
15
14
13:12
IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or Secondary decode.
The IDE I/O Space Enable bit in the Command register must be set for this bit to have any effect.
Additionally, separate configuration bits are provided (in the IDE I/O Configuration register) to
individually disable the primary or secondary IDE interface signals, even if the IDE Decode Enable
bit is set.
0 = Disable.
1 = Enables the ICH4 to decode the associated Command Blocks (1F0–1F7h for primary,
170–177h for secondary) and Control Block (3F6h for primary and 376h for secondary).
This bit effects the IDE decode ranges for both legacy and native-Mode decoding. It also effects the
corresponding primary or secondary memory decode range for IDE Expansion.
Drive 1 Timing Register Enable (SITRE) — R/W.
0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.
1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1.
IORDY Sample Point (ISP) — R/W. The setting of these bits determine the number of PCI clocks
between IDE IOR#/IOW# assertion and the first IORDY sample point.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
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Intel^® 82801DB ICH4 Datasheet