82801DB Datasheet, PDF (223/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.18.7.1 Format of Slave Write Cycle
The external master performs Byte Write commands to the ICH4 SMBus Slave interface. The
“Command” field (bits 11–18) indicate which register is being accessed. The Data field
(bits 20–27) indicate the value that should be written to that register.
The Write Cycle format is shown in Table 5-93. Table 5-94 provides the values associated with the
registers.
Table 5-93. Slave Write Cycle Format
Bits
Description
Driven by
Comment
1
2–8
9
10
11–18
19
20–27
28
29
Start Condition
Slave Address - 7 bits
Write
ACK
Command
ACK
Register Data
ACK
Stop
External Microcontroller
External Microcontroller
Must match value in Receive Slave Address
register
External Microcontroller Always 0
Intel^® ICH4
This field indicates which register will be
External Microcontroller ^accessed.
See Table 5-94 below for the register definitions
ICH4
External Microcontroller See Table 5-94 below for the register definitions
ICH4
External Microcontroller
Table 5-94. Slave Write Registers
Register
0
1–3
4
5
6–7
8
9–FFh
Function
Command Register. See Table 5-95 for legal values written to this register.
Reserved
Data Message Byte 0
Data Message Byte 1
Reserved
Frequency Straps will be written on bits 3:0. Bits 7:4 should be 0, but will be ignored.
Reserved
NOTE: The external microcontroller is responsible to make sure that it does not update the contents of the data
byte registers until they have been read by the system processor. The ICH4 will overwrite the old value
with any new value received. A race condition is possible where the new value is being written to the
register just at the time it is being read. ICH4 will not attempt to cover this race condition
(i.e., unpredictable results in this case).
Intel^® 82801DB ICH4 Datasheet
223