82801DB Datasheet, PDF (115/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
When ICH4 detects a bus idle condition on the APIC Bus, and it has an interrupt to send over the
APIC bus, it drives a start cycle to begin arbitration by driving bit 0 to a 0 on an APICCLK rising
edge. It then samples bit 1. If Bit 1 was a 0, then a local APIC started arbitration for an EOI
message on the same clock edge that the ICH4 started arbitration. The ICH4 has, thus, lost
arbitration and will stop driving the APIC bus.
If the ICH4 did not see an EOI message start, it will start transferring its arbitration ID, located in
bits [27:24] of its Arbitration ID register (ARBID). Starting in Cycle 2, through Cycle 5, it will tri-
state bit 0, and drive bit 1 to a 0 if ARBID[27] is a 1. If ARBID[27] is a 0, it will also tri-state bit 1.
At the end of each cycle, the ICH4 will sample the state of Bit 1 on the APIC bus. If the ICH4 did
not drive Bit 1 (ARBID[27] = 0), and it samples a 0, then another APIC agent started arbitration for
the APIC bus at the same time as the ICH4, and it has higher priority. The ICH4 will stop driving
the APIC bus. Table 5-18 describes the arbitration cycles.
Table 5-18. Arbitration Cycles
Cycle
Bit 1
1
EOI
2
NOT (ARBID[27])
3
NOT (ARBID[26])
4
NOT (ARBID[25])
5
NOT (ARBID[24])
Bit 0
0
1
1
1
1
Comment
Bit 1 = 1: Normal, Bit 1 = 0: EOI
Arbitration ID. If ICH4 samples a different value than it sent, it
lost arbitration.
5.8.3.3 Bus Message Formats
After bus arbitration, the winner is granted exclusive use of the bus and will drive its message.
APIC messages come in four formats, determined by the Delivery Mode bits. These four messages
are of different length, and are known by all APICs on the bus through the transmission of the
Delivery Mode bits.
Table 5-19. APIC Message Formats
Message
EOI
Short
Lowest Priority
Remote Read
# of
Cycles
14
21
33
39
Delivery Mode
Bits
Comments
xxx
001, 010, 100,
101, 111
001
011
End of Interrupt transmission from Local APIC to I/O APIC
on Level interrupts. EOI is known by the EOI bit at the start
of arbitration.
I/O APIC delivery on Fixed, NMI, SMI, Reset, ExtINT, and
Lowest Priority with focus processor messages.
Transmission of Lowest Priority interrupts when the status
field indicates that the processor does not have focus.
Message from one Local APIC to another to read registers.
Intel^® 82801DB ICH4 Datasheet
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