82801DB Datasheet, PDF (502/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

AC ’97 Modem Controller Registers (D31:F6)
Table 15-3. Modem Registers
Offset Mnemonic
00h
MI_BDBAR
04h
MI_CIV
05h
MI_LVI
06h
MI_SR
08h
MI_PICB
0Ah
MI_PIV
0Bh
MI_CR
10h
MO_BDBAR
14h
MO_CIV
15h
MO_LVI
16h
MO_SR
18h
MI_PICB
1Ah
MO_PIV
1Bh
MO_CR
3Ch
GLOB_CNT
40h
GLOB_STA
44h
ACC_SEMA
Name
Modem In Buffer Descriptor List Base Address
Register
Modem In Current Index Value Register
Modem In Last Valid Index Register
Modem In Status Register
Modem In Position In Current Buffer Register
Modem In Prefetch Index Value Register
Modem In Control Register
Modem Out Buffer Descriptor List Base Address
Register
Modem Out Current Index Value Register
Modem Out Last Valid Register
Modem Out Status Register
Modem In Position In Current Buffer Register
Modem Out Prefetched Index Register
Modem Out Control Register
Global Control
Global Status
Codec Write Semaphore Register
Default
00000000h
00h
00h
0001h
00h
00h
00h
00000000h
00h
00h
0001h
00h
00h
00h
00000000h
00000000h
00h
Access
R/W
RO
R/W
R/WC, RO
RO
RO
R/W
R/W
RO
R/W
R/W
RO
RO
R/W
R/W
RO, R/WC,
R/W
R/W
NOTE:
1. MI = Modem in channel; MO = Modem out channel
Note: Internal reset as a result of D3_HOT to D0 transition will reset all the core well registers except the
registers shared with the AC ’97 Audio controller (GCR, GSR, CASR). All resume well registers
will not be reset by the D3_HOT to D0 transition.
Core Well registers and bits NOT reset by the D3_HOT to D0 transition:
• offset 3Ch–3Fh – bits[6:0] Global Control (GLOB_CNT)
• offset 40h–43h – bits[29,15,11:10] Global Status (GLOB_STA)
• offset 44h – Codec Access Semaphore Register (CAS)
Resume Well registers and bits will NOT be reset by the D3_HOT to D0 transition:
• offset 40h–43h – bits[17:16] Global Status (GLOB_STA)
502
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