82801DB Datasheet, PDF (527/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Electrical Characteristics
Table 17-8. Clock Timings (Sheet 2 of 2)
Sym
Parameter
Min Max
I/O APIC Clock (APICCLK)
fioap
t22
t23
t24
t25
Operating Frequency
High time
Low time
Rise time
Fall time
14.32
12
12
1.0
1.0
33.33
36
36
5.0
5.0
fac97
t26
t27
t28
t29
t30
Operating Frequency
Output Jitter
High time
Low time
Rise time
Fall time
fhi Operating Frequency
t31 High time
t32 Low time
t33 Rise time
t34 Fall time
t35 CLK66 leads PCICLK
AC ’97 Clock (BITCLK)
12.288
750
32.56 48.84
32.56 48.84
2.0
6.0
2.0
6.0
Hub Interface Clock
66
6.0
6.0
0.25 1.2
0.25 1.2
1.0
4.5
t1 Period
t2 High Time
PCI Clock (PCICLK)
30
33.3
12
Unit Notes Figure
MHz
ns
ns
ns
ns
MHz
ps
ns
ns
ns 4
ns 4
MHz
ns
ns
ns
ns
ns 5
ns
ns
17-1
17-1
17-1
17-1
17-1
17-1
17-1
17-1
17-1
17-1
17-1
17-1
17-1
17-1
NOTES:
1. The USBCLK is a 48 MHz that expects a 40/60% duty cycle.
2. USBCLK is a pass-thru clock that is not altered by the ICH4. This frequency tolerance specification is
required for USB 1.1 compliance and is affected by external elements such as the clock generator and the
system board.
3. The maximum high time (t18 Max) provide a simple guaranteed method for devices to detect bus idle
conditions.
4. BITCLK Rise and Fall times are measured from 10%VDD and 90%VDD.
5. This specification includes pin-to-pin skew from the clock generator as well as board skew.
6. SUSCLK duty cycle can range from 30% minimum to 70% maximum.
Intel^® 82801DB ICH4 Datasheet
527