82801DB Datasheet, PDF (508/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

AC ’97 Modem Controller Registers (D31:F6)
15.2.9
GLOB_STA—Global Status Register
I/O Address:
Default Value:
Lockable:
MBAR + 40h
00300000h
No
Attribute:
Size:
Power Well:
RO, R/W, R/WC
32 bits
Core
On reads from a codec, the controller will give the codec a maximum of 4 frames to respond, after
which if no response is received, it will return a dummy read completion to the processor (with all
F’s on the data) and also set the Read Completion Status bit in the Global Status Register.
Reads across DWord boundaries are not supported.
Bit
31:30
29
28
27
26
25
24
23:22
21:20
19:18
17
16
Description
Reserved.
AC_SDIN2 Resume Interrupt (S2RI) — R/WC. This bit indicates that a resume event occurred on
AC_SDIN[2].
0 = Cleared by writing a 1 to this bit position.
1 = Resume event occurred.
This bit is not affected by D3_HOT to D0 Reset.
AC_SDIN2 Codec Ready (S2CR) — RO. Reflects the state of the codec ready bit in AC_SDIN[2].
Bus masters ignore the condition of the codec ready bits, so software must check this bit before
starting the bus masters. Once the codec is “ready”, it must never go “not ready” spontaneously.
0 = Not Ready.
1 = Ready.
Bit Clock Stopped (BCS) — RO. Indicates that the bit clock is not running.
0 = Running. It is cleared if a transition is found on BIT_CLK.
1 = Stopped. This bit is set if the ICH4 detects that there has been no transition on BIT_CLK for
four consecutive PCI clocks.
S/PDIF Interrupt (SPINT) — RO.
0 = When the specific status bit is cleared, this bit will be cleared.
1 = Indicates that the S/PDIF out channel interrupt status bits have been set.
PCM In 2 Interrupt (P2INT) — RO.
0 = When the specific status bit is cleared, this bit will be cleared.
1 = Indicates that one of the PCM In 2 channel status bits have been set.
Microphone 2 In Interrupt (M2INT) — RO.
0 = When the specific status bit is cleared, this bit will be cleared.
1 = Indicates that one of the Mic in channel interrupts status bits has been set.
Sample Capabilities — RO. Indicates the capability to support more greater than 16-bit audio.
00 = Reserved
01 = 16 and 20-bit Audio supported (ICH4 value)
10 = Reserved
11 = Reserved
Multichannel Capabilities — RO. Indicates the capability to support more 4 and 6 channels on PCM
Out.
Reserved.
MD3 — R/W. Power down semaphore for Modem. This bit exists in the suspend well and maintains
context across power states (except G3). The bit has no hardware function. It is used by software in
conjunction with the AD3 bit to coordinate the entry of the two codecs into D3 state.
This bit is not affected by D3_HOT to D0 Reset.
AD3 — R/W. Power down semaphore for Audio. This bit exists in the suspend well and maintains
context across power states (except G3). The bit has no hardware function. It is used by software in
conjunction with the MD3 bit to coordinate the entry of the two codecs into D3 state.
This bit is not affected by D3_HOT to D0 Reset.
508
Intel^® 82801DB ICH4 Datasheet