82801DB Datasheet, PDF (61/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Intel^® ICH4 Power Planes and Pin States
Table 3-4. Power Plane and States for Output and I/O Signal (Sheet 3 of 4)
Signal Name
Power
Plane
During
PCIRST#⁴ /
RSMRST#^5,7
Immediately
after
PCIRST#⁴ /
RSMRST#⁵
S1
Power Management
SLP_S3#
Resume I/O
Low
High
High
SLP_S4#
Resume I/O
Low
High
High
SLP_S5#
Resume I/O
Low
High
High
SUS_STAT#
Resume I/O
Low
High
High
SUSCLK
Resume I/O
Running
Processor Interface
A20M#
CPU I/O See Note 1
High
High
CPUPWRGD
Main I/O See Note 3
High-Z
High-Z
CPUSLP#
CPU I/O
High
High
Defined
IGNNE#
CPU I/O See Note 1
High
High
INIT#
CPU I/O
High
High
High
INTR
CPU I/O See Note 1
Low
Low
NMI
CPU I/O See Note 1
Low
Low
SMI#
CPU I/O
High
High
High
STPCLK#
CPU I/O
High
High
Low
SMBus Interface
SMBCLK, SMBDATA Resume I/O
High-Z
High-Z
Defined
System Management Interface
SMLINK[1:0]
Resume I/O
High-Z
High-Z
Defined
Miscellaneous Signals
SPKR
Low with
Main I/O Internal Pull-
Low
Down
Defined
AC ’97 Interface
AC_RST#
Resume I/O
Low
Low
Cold Reset
Bit (High)
AC_SDOUT
Main I/O
Low
Running
Low
AC_SYNC
Main I/O
Low
Running
Low
S3
Low
High
High
Low
Off
Off
Off
Off
Off
Off
Off
Off
Off
Defined
Defined
Off
Low
Off
Off
S4/S5
Low
Low
Note 6
Low
Off
Off
Off
Off
Off
Off
Off
Off
Off
Defined
Defined
Off
Low
Off
Off
Intel^® 82801DB ICH4 Datasheet
61