82801DB Datasheet, PDF (152/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.12.10.4 Controlling Leakage and Power Consumption during Low-Power
States
To control leakage in the system, various signals tri-state or go low during some low-power states.
General principles:
• All signals going to powered down planes (either internally or externally) must be either tri-
stated or driven low.
• Signals with pull-up resistors should not be low during low-power states. This is to avoid the
power consumed in the pull-up resistor.
• Buses should be halted (and held) in a known state to avoid a floating input (perhaps to some
other device). Floating inputs can cause extra power consumption.
Based on the above principles, the following measures are taken:
• During S3 (STR), all signals attached to powered down planes will be tri-stated or driven low.
5.12.11 Clock Generators
The clock generator is expected to provide the frequencies shown in Table 5-49.
Table 5-49. Intel^® ICH4 Clock Inputs
Clock
Domain
Frequency Source
Usage
CLK66
PCICLK
CLK48
CLK14
AC_BIT_CLK
APICCLK
LAN_CLK
66 MHz
33 MHz
48 MHz
14.318 MHz
12.288 MHz
16.67 MHz
or 33 MHz
0.8 to
50 MHz
Main Clock
Generator
Main Clock
Generator
Main Clock
Generator
Main Clock
Generator
AC ’97
Codec
Main Clock
Generator
LAN
Connect
Should be running in all Cx states. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
Free-running PCI Clock to ICH4. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
Used by USB controllers. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
Used by ACPI timers. Stopped in S3 ~ S5 based on SLP_S3#
assertion.
AC-link. Control policy is determined by the clock source.
Used for ICH4-processor interrupt messages. Should be
running in C0, C1 and C2. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
LAN Connect link. Control policy is determined by the clock
source.
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Intel^® 82801DB ICH4 Datasheet