82801DB Datasheet, PDF (40/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Signal Description
2.3
EEPROM Interface
Table 2-3. EEPROM Interface Signals
Name
EE_SHCLK
EE_DIN
EE_DOUT
EE_CS
Type
O
I
O
O
Description
EEPROM Shift Clock: This signal is the serial shift clock output to the
EEPROM.
EEPROM Data In: This signal transfers data from the EEPROM to the Intel^®
ICH4. This signal has an integrated pull-up resistor.
EEPROM Data Out: EE_DOUT transfers data from the ICH4 to the EEPROM.
EEPROM Chip Select: EE_CS is the chip select signal to the EEPROM.
2.4
Firmware Hub Interface
Table 2-4. Firmware Hub Interface Signals
Name
Type
Description
FWH[3:0] /
LAD[3:0]
FWH[4] /
LFRAME#
I/O Firmware Hub Signals: FWH[3:0] are muxed with LPC address signals.
I/O Firmware Hub Signals: FWH[4] is muxed with the LPC LFRAME# signal.
2.5
PCI Interface
Table 2-5. PCI Interface Signals (Sheet 1 of 3)
Name
AD[31:0]
C/BE[3:0]#
Type
I/O
I/O
Description
PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During
the first clock of a transaction, AD[31:0] contain a physical address (32 bits).
During subsequent clocks, AD[31:0] contain data. The Intel^® ICH4drives all 0s
on AD[31:0] during the address phase of all PCI Special Cycles.
Bus Command and Byte Enables: The command and byte enable signals
are multiplexed on the same PCI pins. During the address phase of a
transaction, C/BE[3:0]# define the bus command. During the data phase, C/
BE[3:0]# define the Byte Enables.
C/BE[3:0]#
0000
0001
0010
0011
0110
0111
1010
1011
1100
1110
1111
Command Type
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
Memory Read Line
Memory Write and Invalidate
All command encodings not shown are reserved. The ICH4 does not decode
reserved values, and therefore will not respond if a PCI master generates a
cycle using one of the reserved values.
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Intel^® 82801DB ICH4 Datasheet