82801DB Datasheet, PDF (463/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

SMBus Controller Registers (D31:F3)
13.2.14 SMBUS_PIN_CTL—SMBUS Pin Control Register
Register Offset: 0Fh
Default Value: See below
Attribute:
Size:
R/W, RO
8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit
Description
7:3 Reserved
SMBCLK_CTL — R/W.
0 = ICH4 will drive the SMBCLK pin low, independent of what the other SMB logic would otherwise
2
indicate for the SMBCLK pin.
1 = The SMBCLK pin is not overdriven low. The other SMBus logic controls the state of the pin.
(Default)
SMBDATA_CUR_STS — RO. This pin returns the value on the SMBDATA pin. This allows software to
read the current state of the pin. Default value is dependent on an external signal level.
1 _{0 = Low}
1 = High
SMBCLK_CUR_STS — RO. This pin returns the value on the SMBCLK pin. This allows software to
read the current state of the pin. Default value is dependent on an external signal level.
0 _{0 = Low}
1 = High
13.2.15 SLV_STS—Slave Status Register
Register Offset: 10h
Default Value: 00h
Attribute:
Size:
R/WC
8 bits
Note: This register is in the resume well and is reset by RSMRST#.
All bits in this register are implemented in the 64 kHz clock domain. Therefore, software must poll
this register until a write takes effect before assuming that a write has completed internally.
Bit
Description
7:1 Reserved
HOST_NOTIFY_STS — R/WC. The ICH4 sets this bit to a 1 when it has completely received a
successful Host Notify Command on the SMLink pins. Software reads this bit to determine that the
source of the interrupt or SMI# was the reception of the Host Notify Command. Software clears this bit
0 after reading any information needed from the Notify address and data registers by writing a 1 to this
bit. Note that the ICH4 will allow the Notify Address and Data registers to be over-written once this bit
has been cleared. When this bit is 1, the ICH4 will NACK the first byte (host address) of any new “Host
Notify” commands on the SMLink. Writing a 0 to this bit has no effect.
Intel^® 82801DB ICH4 Datasheet
463