82801DB Datasheet, PDF (299/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.1.17
9.1.18
SERIRQ_CNTL—Serial IRQ Control (LPC I/F—D31:F0)
Offset Address: 64h
Default Value: 10h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8 bit
Core
Bit
Description
Serial IRQ Enable (SIRQEN) — R/W.
7 0 = The buffer is input only and internally SERIRQ will be a 1.
1 = Serial IRQs will be recognized. The SERIRQ pin will be configured as SERIRQ.
Serial IRQ Mode Select (SIRQMD) — R/W.
0 = The serial IRQ machine will be in quiet mode.
1 = The serial IRQ machine will be in continuous mode.
6
NOTE: For systems using Quiet Mode, this bit should be set to 1 (Continuous Mode) for at least one
frame after coming out of reset before switching back to Quiet Mode. Failure to do so will
result in the Intel^® ICH4 not recognizing SERIRQ interrupts.
Serial IRQ Frame Size (SIRQSZ) — R/W. Fixed field that indicates the size of the SERIRQ frame. In
5:2 the ICH4, this field needs to be programmed to 21 frames (0100). This is an offset from a base of 17
which is the smallest data frame size.
Start Frame Pulse Width (SFPW) — R/W. This is the number of PCI clocks that the SERIRQ pin will
be driven low by the serial IRQ machine to signal a start frame. In continuous mode, the ICH4 will
drive the start frame for the number of clocks specified. In quiet mode, the ICH4 will drive the start
frame for the number of clocks specified minus one, as the first clock was driven by the peripheral.
1:0
00 = 4 clocks
01 = 6 clocks
10 = 8 clocks
11 = Reserved
PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
PIRQE–68h, PIRQF–69h,
PIRQG–6Ah, PIRQH–6Bh
80h
No
Attribute:
Size:
Power Well:
R/W
8 bit
Core
Bit
Description
Interrupt Routing Enable (IRQEN) — R/W.
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0].
1 = The PIRQ is not routed to the 8259.
7
NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are being used. The
value of this bit may subsequently be changed by the OS when setting up for I/O APIC
interrupt delivery mode.
6:4 Reserved
IRQ Routing — R/W. (ISA compatible)
0000 = Reserved 1000 = Reserved
0001 = Reserved 1001 = IRQ9
0010 = Reserved 1010 = IRQ10
3:0 _{0011 = IRQ3}
1011 = IRQ11
0100 = IRQ4
1100 = IRQ12
0101 = IRQ5
1101 = Reserved
0110 = IRQ6
1110 = IRQ14
0111 = IRQ7
1111 = IRQ15
Intel^® 82801DB ICH4 Datasheet
299