82801DB Datasheet, PDF (381/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.10.5
9.10.6
GPI_INV—GPIO Signal Invert Register
Offset Address:
Default Value:
Lockable:
GPIOBASE +2Ch
00000000h
No
Attribute:
Size:
Power Well:
R/W
32-bit
See bit description
Bit
Description
31:14,
10:9
13:11, 8
7:0
Reserved
GP_INV[n] — R/W. These bits are used to allow both active-low and active-high inputs to cause
SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least 2 PCI
clocks to ensure detection by the Intel^® ICH4. In the S3, S4 or S5 states the input signal must be
active for at least 2 RTC clocks to ensure detection. The setting of these bits will have no effect if
the corresponding GPIO is programmed as an output. These bits correspond to GPIO that are in
the Resume well, and will be reset to their default values by RSMRST# or a write to the CF9h
register.
0 = The corresponding GPI_STS bit will be set when the ICH4 detects the state of the input pin
to be high.
1 = The corresponding GPI_STS bit will be set when the ICH4 detects the state of the input pin
to be low.
GP_INV[n] — R/W. These bits are used to allow both active-low and active-high inputs to cause
SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least 2 PCI
clocks to ensure detection by the ICH4. The setting of these bits will have no effect if the
corresponding GPIO is programmed as an output. These bits correspond to GPIO that are in the
Core well, and will be reset to their default values by PCIRST#.
0 = The corresponding GPI_STS bit will be set when the ICH4 detects the state of the input pin
to be high.
1 = The corresponding GPI_STS bit will be set when the ICH4 detects the state of the input pin
to be low.
GPIO_USE_SEL2—GPIO Use Select 2 Register
Offset Address:
Default Value:
Lockable:
GPIOBASE +30h
00000FFFh
No
Attribute:
Size:
Power Well:
R/W
32-bit
Core
Bit
Description
GPIO_USE_SEL2[43:32]— R/W. Each bit in this register enables the corresponding GPIO (if it
exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
31:0 ^NOTES:
1. The following bits are not implemented because there is no corresponding GPIO: 31:12
2. If GPIO[n] does not exist, then the bit in this register will always read as 0 and writes will have
no effect.
After a full reset (RSMRST#) all multiplexed signals in the resume and core wells are configured
as their native function rather than as a GPIO. After just a PCIRST#, the GPIO in the core well are
configured as their native function.
Intel^® 82801DB ICH4 Datasheet
381