82801DB Datasheet, PDF (538/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Electrical Characteristics
Table 17-20. Power Management Timings
Sym
Parameter
Min
t181
VccSus active to SLP_S5#, SUS_STAT# and
PCIRST# active
t182 RSMRST# inactive to SUSCLK running, SLP_S5#
t183 inactive
t183a SLPS5# inactive to SLP_S4# inactive
1
t183b SLPS4# inactive to SLP_S3# inactive
1
t184
Vcc active to STPCLK# and CPUSLP# inactive, and
processor Frequency Strap signals high
PWROK and VRMPWRGD active and
t185 SYS_RESET# inactive to SUS_STAT# inactive and 32
processor Frequency Straps latched to Strap Values
t186
Processor Reset Complete to Frequency Strap
signals unlatched from Strap Values
7
t187 STPCLK# active to Stop Grant cycle
N/A
t188 Stop Grant cycle to CPUSLP# active
60
t189 S1 Wake Event to CPUSLP# inactive
1
t190 CPUSLP# inactive to STPCLK# inactive
3.87
t192 CPUSLP# active to SUS_STAT# active
2
t193 SUS_STAT# active to PCIRST# active
9
t194 PCIRST# active to SLP_S3# active
1
t194a SLP_S3# active to SLP_S4# active
1
t195 SLP_S4# active to SLP_S5# active
1
t196 SLP_S3# active to PWROK, VRMPWRGD inactive
0
t197
PWROK, VRMPWRGD inactive to Vcc supplies
inactive
20
t198 Wake Event to SLP_S5# inactive
1
t198a Wake Event to SLP_S4# inactive (S4 Wake)
1
t198b Wake Event to SLP_S3# inactive (S3 Wake)
1
t198d SLP_S5# inactive to SLP_S4# inactive
1
t198e SLP_S4# inactive to SLP_S3# inactive
1
t204 CPU I/F signals latched prior to STPCLK# active
0
t205 Break Event to STPCLK# inactive
30
t206 STPCLK# inactive to processor I/F signals unlatched 240
t220
THRMTRIP# active to SLP_S3#, SLP_S4#,
SLP_S5# active
Max Units
50
ns
110
ms
2 RTCCLK
2 RTCCLK
50
ns
38 RTCCLK
9
CLK66
N/A
63 PCICLK
25 PCICLK
245
µs
4 RTCCLK
21 RTCCLK
2 RTCCLK
2 RTCCLK
2 RTCCLK
ms
ns
10
10
10
2
2
4
3120
1880
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
CLK66
ns
ns
2 PCI CLK
Notes
7
1
2
3
4
4
1
1
1
1
1, 6
5
1
1
1
1
1
2
Fig
17-20
17-20
17-20
17-20
17-20
17-20
17-20
17-21
17-20
17-21
17-20
17-20
17-21
17-21
17-21
17-21
17-21
17-21
17-21
17-21
17-21
17-22
17-22
17-22
NOTES:
1. These transitions are clocked off the internal RTC. 1 RTC clock is approximately 32 µs.
2. This transition is clocked off the 66 MHz CLK66. 1 CLK66 is approximately 15 ns.
3. The ICH4 STPCLK# assertion will trigger the processor to send a stop grant acknowledge cycle. The timing
for this cycle getting to the ICH4 is dependant on the processor and the memory controller.
4. These transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30 ns.
5. The ICH4 has no maximum timing requirement for this transition. It is up to the system designer to determine
if the SLP_S3#, SLP_S4# and SLP_S5# signals are used to control the power planes.
538
Intel^® 82801DB ICH4 Datasheet