82801DB Datasheet, PDF (469/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

AC ’97 Audio Controller Registers (D31:F5)
14.1.3
PCICMD—PCI Command Register (Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
04–05h
0000h
No
Attribute:
Size:
Power Well:
R/W, RO
16 bits
Core
PCICMD is a 16-bit control register. Refer to the PCI 2.2 specification for complete details on each
bit.
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Description
Reserved. Read 0.
Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0.
SERR# Enable (SERR_EN) — RO. Not implemented. Hardwired to 0.
Wait Cycle Control (WCC) — RO. Not implemented. Hardwired to 0.
Parity Error Response (PER) — RO. Not implemented. Hardwired to 0.
VGA Palette Snoop (VPS) — RO. Not implemented. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE) — RO. Not implemented. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Not implemented. Hardwired to 0.
Bus Master Enable (BME) — R/W. This bit controls standard PCI bus mastering capabilities.
0 = Disable (Default).
1 = Enable
Memory Space Enable (MSE) — R/W. This bit enables memory space addresses to the AC ’97
Audio controller. (Default=0).
0 = Disable (Default)
1 = Enable
I/O Space Enable (IOSE) — R/W. This bit controls access to the AC ’97 Audio controller I/O space
registers.
0 = Disable (Default)
1 = Enable access to I/O space. The Native PCI Mode Base Address register should be
programmed prior to setting this bit.
NOTE: This bit becomes write-able when the IOSE bit in offset 41h is set. If at any point software
decides to clear the IOSE bit, software must first clear the IOS bit first.
Intel^® 82801DB ICH4 Datasheet
469